高速高精度采样/保持电路理论模型与技术实现

【作者】 吴霜毅；

【导师】 杨谟华；

【作者基本信息】 电子科技大学 ， 微电子学与固体电子学， 2007， 硕士

【摘要】 采样/保持电路(S/H)是模拟-数字转换电路(ADC)中的关键单元电路,而ADC则是VLSI数字信号处理系统中的重要模块。随着通信系统和消费类电子设备的发展,需要ADC具有更快的采样速度、更高的采样精度和更低的功耗,同样也需要其前端的采样/保持电路具有高速、高精度、低功耗的性能。本文分别从S/H架构、ADC系统中的S/H、采样开关电路及误差、双采样多通道S/H和运放优化技术等方面研究和探讨了理论模型和相应的电路实现途径,同时基于中芯国际0.18μm混合信号CMOS工艺设计了12bit、100MSample/s (100MSPS)的S/H原型验证电路。主要内容和结果包括:1)系统阐述和分析了采样/保持电路的各种架构,指明对于12bit采样精度和100MHz采样速度指标,基于开关电容的电容翻转型闭环采样/保持电路架构可以保证电路性能的可实现性和可靠性。2)从ADC系统的角度深入研究了采样/保持电路的性能指标和电路重要参数与Pipeline ADC系统的相互制约关系。结合ADC系统架构、噪声容限和工艺匹配性,确定了采样电容的取值和运放的输入失调电压。3)建立了采样开关的等效电路模型和误差源模型,重点研究了电荷注入误差、非线性模拟带宽误差和采样时刻不确定性误差;针对典型误差源给出了相应的改进电路;基于Matlab仿真环境,对各电路和误差源进行了时域和频谱分析。仿真结果显示,0.637ps的jitter噪声给S/H引入约-120dB的噪声平台;全差分栅压自举采样开关的线性度可达到-100dB;所采用的采样电容的失配导致的二次谐波失真低于-138dB。4)探讨了双采样电容翻转型电路的原理、电路架构和误差源。基于频域重点分析了双采样通道间的失调、失配和时钟歪斜误差,并进一步研究了双采样电路与开关电容负载间的电荷共享效应及其对输出信号建立特性的影响。5)分别建立了运放输出的大信号建立模型和小信号快速建立模型,通过系统分析确定了满足100MHz采样频率的运放单位增益带宽不低于267MHz,相位裕度为74°;并依据采样/保持电路的性能指标确定了运放的其他指标和功耗。6)基于中芯国际0.18μm CMOS数模混合标准工艺,设计仿真了具有12bit、100MHz的双采样电容翻转型S/H电路,电源电压3.3V,差分信号摆幅2V。仿真结果表明,S/H的保持信号建立时间为9.28ns,建立精度312μV,增益误差1.23mV,SFDR为92.34dB,功耗为39.93mW。更多还原

【Abstract】 Sample and Hold (S/H) circuit is the key front-end block of Analog-to-Digital converters (ADCs), while ADCs are of importance in modern VLSI digital signal processing systems. The increasing digitalization in all spheres of electronics applications, from telecommunications systems to consumer electronics appliances, requires ADCs with a higher sampling rate, higher resolution, and lower power consumption. Hence the same performance requirements come to the S/H circuits.This thesis studies the academic models and technical implementation schemes for high speed, high resolution S/H circuits. It covers the S/H architecture, the relationship between S/H and Pipeline ADC, sampling switch with error sources, double sampling, and optimization on settling features of operational amplifier. Finally, a 12bit 100MSample/s S/H prototype circuits is designed based on SMIC 0.18μm CMOS mixed-signal process. The details include:1) The main architectures of S/H circuits are discussed, and it specifies that the switched capacitor close-loop flip-over S/H topology can achieve 12bit 100MSample/s performance under sufficient reliability and realizability.2) The relationship between pipeline ADC architecture and S/H performances is examined, especially on noise-power trade-off. The sampling capacitor value and the input offset voltage of Op-Amp are specified, with the consideration of the noise transfer function and tolerance, stage resolution distribution theory in pipeline ADC and process mismatch.3) Established the equivalence circuit and error sources model of sampling switches, where the later emphasizes the charge injection, nonlinear analog bandwidth and sampling moment uncertainty. Then the error-corresponding performance-improved circuits are examined. The circuits and error sources are analyzed in both time and frequency domain with Matlab simulation environment. The results show that: 0.637ps clock rms jitter brings -120dB noise to the S/H; the full differential bootstrapped switch achieves -100dB linearity; and the mismatch between sampling capacitor leads -138dB second order distortion.4) An analysis of non-idealities in double-sampling is presented. The mismatch, offset and clock skew error of parallel signal paths are discussed in both time and frequency domain. The charge sharing effects on output signal settling, which is between double sampling circuits and switch-capacitor load, are stressed on.5) The op amp output slew model and fast settling model is built, drawing the conclusion that the UGB should be larger than 267MHz, where the fast-settling phase margin is about 74?.6) Based on SMIC 0.18μm CMOS mixed-signal process, a 12bit 100MSample/s S/H prototype circuits is designed with HSpice simulation environment. The simulation results show that the settling time is 9.28ns, with pedestal error of 312μV, gain error of 1.23mV, and the SFDR of 92.34dB. The total power consumption of the S/H is 39.93mW with 3.3V power supply.更多还原