大容量扩频通信机关键技术FPGA实现技术研究

【作者】 周屹；

【导师】 李少谦；

【作者基本信息】 电子科技大学 ， 通信与信息系统， 2007， 硕士

【摘要】 无线通信因为发射功率小,设备简单,通信方式灵活,抗毁性强等优点成为无线部门和其他远距离通信和指挥的重要工具。就通信的顽固性,机动性和灵活性而言,无线通信也具有一定的的优越性。在无线通信系统的研制中,通信速率与抗干扰性能是衡量通信系统水平的关键。大容量扩频通信机研制的项目在这两方面都达到了国内先进水平。本文作为大容量扩频通信机项目的关键组成部分之一,研究了使用现场可编程器件(FPGA)来设计与实现时间与频率同步技术,数字上变频与下变频技术以及FPGA与终端、DSP、A/D、D/A的接口技术等相关问题。论文主要内容如下:针对时间与频率同步技术,本文首先介绍了一种适合本系统的时间与频率同步算法。然后,将同步过程分为基于短序列的时间同步、基于长序列的时间同步结束检测、基于长序列的频率同步三个部分详细讨论其实现技术。最后,通过比较在DSP中与在FPGA中所实现的同步的性能,结合所使用资源的分析,证明了在FPGA中实现对时间与频率同步技术是可行的。针对数字中频实现技术,本文首先介绍了其基础理论。然后将整个中频系统划分为CIC滤波器、CIC补偿滤波器、混频电路分别讨论其实现技术。通过理论分析和仿真确定了CIC滤波器的参数;讨论了CIC补偿滤波器中滤波器阶数对补偿性能的影响;分析比较了混频电路部分的实现方式,最后采用查表法实现并分析了其性能。在本系统中,由于需要终端、DSP、FPGA等的相互配合完成整个通信任务,FPGA与外部器件的接口是实现的关键问题之一,依据系统的具体情况,本文提出了FPGA与终端、DSP接口的实现要求并最终给出了解决方案。大容量扩频通信机系统已经完成室内有线及室外无线的通信测试,测试结果满足系统要求。这进一步证明了本文所描述的FPGA实现在实际应用中的可行性。更多还原

【Abstract】 Because of having many merits such as small transmit power, simple equipment, agility of communication mode, and strong anti-destroied ability, wireless communication becomes an important tool of wireless department and other telecommunication and command. As for communicational hardness, flexibility and agility, wireless communication also holds its unsurpassed advantages. Communication rate and anti-jamming ability are two keys to weight the level of a communication system. The system Large Capacity Spectrum Spreading Communication System developed by us has been achieved domestic high level at those two aspects.AS a key part of Large Capacity Spectrum Spreading Communication System project, this thesis investigates the design and realization of aynchronization technique in time and frequence domain, Digital Down Converter and Digital Up Converter technique, and interface technique between FPGA and terminal,DSP,A/D,D/A, and some other correlation problems using FPGA.The main contents of this dissertation are summarized as following:Aiming at time and frequency synchronization technique, after introducing the algorithm of time and frequency synchronization which adapt to our system, this thesis devides the synchronization process into three parts to discuss in detail, including time synchronization based on short serial, detecting the end of time synchronization based on long serial, and frequence synchronization based on long serial.This thesis introduces the basis theory of digital intermediate frequency, partitions the whole intermediate frequency system into CIC Filter, CIC Compensation Filter and mixing circuit, and discusses their realization respectively. According to theory analyse and simulation, we’ve confirmed parameters of CIC Filter, investigated the affection to the performance of compensation caused by filter steps in CIC Filter, and analysed both mixing part and its performance.Interface between FPGA and exterior device is a main problem of realizing this system. Based on the embody request, this thesis presents the purpose which the interface between FPGA and terminal, DSP want to achieve. Finnally, a solution scheme is given.更多还原