基于sigma-delta的音频codec的设计与实现

【作者】 王珩；

【导师】 陈勇；

【作者基本信息】 电子科技大学 ， 微电子学与固体电子学， 2007， 硕士

【摘要】 本文研究了基于Σ-Δ噪声整形技术和过采样技术的音频codec电路。其核心模块为过采样Σ-Δ的数模、模数转换器和过采样滤波器。其中由模拟电路实现的ADCΣ-Δ调制器在获得高分辨率的同时模拟器件不需要很高的匹配率;由数字电路实现的DACΣ-Δ调制器和过采样滤波器可充分利用现代VLSI的高速、高集成度、低成本等优点。本文重点研究了音频codec中数字电路部分,即过采样滤波器和DACΣ-Δ调制器的设计与实现。为了用较简单的电路实现较高的SNR,DACΣ-Δ调制器选用1bit单环结构,通过切比雪夫高通滤波器逼近来求解系统参数,并优化系统零极点,以解决1bit单环结构Σ-Δ调制器中输入信号动态范围和系统稳定性之间的矛盾。系统中过采样滤波器分为ADC中抽取滤波器和DAC中的插值滤波器。过采样滤波器采用多级化实现,有效地减少了滤波器的存储量和运算量;在ADC抽取滤波器中,采用了去直流滤波器滤除ADCΣ-Δ调制器中引入的直流电平;在DAC插值滤波器组中,采用了FIR滤波器的多相结构实现FIR插值滤波器。针对本项目中电路时序比较容易满足,而对芯片面积有较严格要求的特点,采用了多种方式来优化电路面积:左右声道数据处理共享组合电路;滤波器实现采用顺序执行方式,并合理安排乘累加单元处理信号的时序,实现左右声道和多级滤波器之间能最大化共享乘累加单元。为满足不同客户对codec的要求,要求音频codec能支持从8k至48k的多种采样率,数字音频的位数可以是16位至24位,并支持I2S、DSP、左对齐、右对齐四种数字音频接口。经过系统设计,RTL代码编写,DFT设计,综合,布局布线,静态时序分析和时序验证等流程,最终提交数字电路版图,并采用SMIC 0.18μm标准CMOS工艺流片。该芯片测试结果基本达到预设指标。更多还原

【Abstract】 The audio codec is based on sigma-delta modulation and over-sampling signal process. Analog-to-digital&digital-to-analog converter based on sigma-delta modulation and over-sampling filter are the main difficults of the design.ADC sigma-delta modulator implemented by analog circuit could gain high accuracy and be quite insensitive to mismatch and other circuit imperfections; DAC sigma-delta modulator and over-sampling filter implemented by digital curcuit could exploit the enhanced speed, curcuit density and low cost of modern VLSI technologies.This paper will pay attention to designing and implementing digital circuit of audio codec --- DAC sigma-delta modulator and over-sampling filter.In order to achieve higher SNR by the simple architecture, we choose the 1bit single-loop sigma-delta modulator.We could use Chebyshev high filter’s function to gain the system parameters, and optimize the locations of zeros and poles for DAC sigma-delta modulator,which both are stable modulators and the input signal of the modulators can achieve maximum.Decimator for ADC and interpolator for DAC make up of oversampling filter.Implement of multi-level filter could save the quantity of calculate and storage for FIR.A novel method of removing DC is used in decimator.Multi-phase architecture of filter is used in interpolator.Because timing is easy to satisfy, how to save areas is taken as the first considered factor.By the methods of multi-level filter, left and right channel sharing combinational logic module and using TDMA in the sequential process of filters, the circuit area could be reduced observably.In order to satisfy most customers’need, the codec support the sample rates from 48k to 8k, there are 9 sample rates; the data-width can be choosed from 16bits to 24bits; there are 4 modes for digital audio interface.After the flow of system design, rtl coding, DFT design, DC systhesis, place and route, STA, and timing verfication, the digital layout is shown in the end. This chip has been implemented in the SMIC 0.18μm CMOS process. Test result shows that the chip has achieved the design target.更多还原