阵列相位感应测井仪（APIL）接收机设计

【作者】 徐鹏；

【导师】 师奕兵；

【作者基本信息】 电子科技大学 ， 测试计量技术与仪器， 2007， 硕士

【摘要】 本课题研究的阵列相位感应测井仪(APIL：Array Phase Induction logging)属于新一代数字阵列电磁波电阻率测井仪。该仪器由5个发射线圈和10个接收线圈构成发射—接收阵列，工作频率为0.4MHz、0.8MHz、1.6MHz、3.2MHz、6.4MHz，能提供5条不同探测深度的相位差／电阻率曲线。它基于电磁场论和波动学理论，不测量接收信号的绝对值，只测相位差，而这个相位差与井眼周围地层的电导率直接相关。这种方法消除了传统意义上传播效应，即趋肤效应的影响，拓展了电阻率的测量范围，减少了井眼、泥浆及其它因素的影响。在径向探测深度增加的同时，不牺牲纵向分辨率，可靠地获取原状地层参数信息。本文主要阐述了基于微弱信号调理和直接数字频率合成技术的阵列相位感应测井仪接收机的硬件设计原理，给出并实现了设计方案。本论文着重阐述了可编程逻辑器件内的逻辑设计，直接数字频率合成的硬件结构，微弱信号调理电路的设计方案和线圈谐振匹配网络的设计实现，还对与硬件密切相关的CPU控制命令和地面仿真测试系统做了简要介绍。本论文的主要内容包括：第一章中，对测井技术和电法测井国内外的发展趋势做了介绍，并阐述了本课题的研究内容。第二章中简述了本课题的理论依据，按照本研究课题的设计要求解析了硬件设计结构和模块划分。第三章针对线圈谐振的基本特性，重点对线圈接收到的信号的提取方法、信号的长距离传输进行了讨论；针对微弱信号处理的特点着重对信号调理电路的实现原理和电路结构作了具体的讨论。第四章根据混频电路对本振信号源的需要，重点阐述了本振信号源设计的目标、电路原理和结构，以及FPGA片内的逻辑设计；并讨论了仪器工作状态的控制逻辑，还详细讨论了相位差计算的逻辑固件。第五章主要讨论了仪器设计中的调试、实验以及需要做的改进。第六章对本课题作了总结。实际测试表明，该接收机满足阵列相位感应测井仪的要求。课题已顺利通过验收。更多还原

【Abstract】 The researched equipment in this dissertation is a new generation one of Array Phase Induction logging. It consists of an array of 5 emitters and 10 receivers, working frequencies are 0.4MHz, 0.8MHz, 1.6MHz, 3.2MHz, 6.4MHz and respectively can provide 5 different depth detecting phase curves. The work of the equipment is based on electromagnetic field theory and undulation theory, and it does not measure the absolute quantity but measure the phase difference of the two signals. The phase difference is related to the conductance of the rocks nearby in the well hole. This approach reduces the trouble of diffusion and widens the conductance mearsuring field. And it reduces the influence of the well hole, slurry on the measured results. And the radial detection depth increases but the vertical resolution does not decrease, so we can obtain the imformation of the original stratum.The dissertation mainly illustrates the Array Phase Induction logging receiver’s hardware design and its implementation scheme based on the techniques of faintness signal adjusting and Direct Digtal Synthesis. According to the emphesis and difficulty, the dissertation expatiates on the logic design of the FPGA, the hardware architecture of the DDS design, faintness signal adjusting circuit design and the implementation of winding resonance circuit. The dissertation also gives a brief description of CPU instruction and testing system. This dissertation includes:Chapter 1 gives a introduction of logging and electric logging and introduces the project. Chapter 2 expatiates on the theory of the project and the architecture of project. Chapter 3 gives a discussion in details on signal’s picking up from the winding wire and the signal’s long distance transmission. The implementation and the architecture of the signal’s adjusting circuit are also discussed in this chapter. Chapter 4 mainly discusses the goal of signal generation circuit, the architecture of signal generation circuit, the principle of signal generation circuit and the FPGA’s internal logic design, discusses the equipment status control logic and the firmware used to detect the phasic difference. Chapter 5 discusses the debugging, the experiments and something needs to be improved. Chapter 6 is the summary of the dissertation. Experiments show that, the designed receiver satisfied the requirements of Array Phase Induction logging and has been checked and accepted by the project sponsor.更多还原