【作者】 薛骏；

【导师】 时龙兴；

【作者基本信息】 东南大学 ， 电路与系统， 2005， 硕士

【摘要】 当前SoC系统中为了提高系统性能都会内嵌各种存储器,尤其是静态存储器(SRAM)电路由于兼容标准的CMOS工艺成为嵌入式存储器的首选。这些存储单元不论是在芯片面积还是功耗上都占有非常大的比重,所以它们的性能决定了整个嵌入式系统的性能。由此可见,在SoC系统中设计一块高性能的SRAM电路是至关重要的。SoC系统要求SRAM电路有较低的功耗、较快的访问速度和较小的芯片面积,不过通过分析可以知道在提高电路的一个方面性能的同时会降低另一方面的性能,所以必须针对系统的要求评估各个性能参数的变化趋势,从而得到最优化的设计方案。本文从分析SRAM电路的结构入手,详细分析了SRAM电路各个子电路的工作状态,并采用电路分析和仿真的方法建立了电路的功耗、访问速度和芯片面积模型。然后将该模型应用于ARM720T内核的SRAM电路设计中,提出了最优化的电路设计方案。最后采用该模型设计了Cache电路中容量为8KB的SRAM电路。本文还对8KB SRAM电路做了结构上的优化,采用了两种电路改进的方法来改进电路的性能:低电压位线摆幅技术和地址转换侦测技术。低电压位线摆幅技术的实现通过改进预充电电路的结构,降低列未选中单元的位线摆幅,从而降低读写功耗。地址转换侦测技术改进了译码电路的结构,引入了地址转换侦测脉冲信号,减少了字线选通的时间,从而降低列选中单元的位线摆幅。8KB SRAM电路采用全定制设计方式实现,通过了Chart 0.25um工艺和SMIC 0.18um工艺下的前端原理图仿真和后端版图仿真,在Chart 0.25um工艺下芯片面积为1.92mm2,访问时间为1.8ns,读功耗为16.4mW,写功耗为13.3mW。SMIC 0.18工艺下芯片面积为1.38mm2,访问时间为1.7ns,读功耗为7.5mW,写功耗为6.25mW,所有性能参数都符合了设计要求。通过本文对于SRAM电路各个性能参数模型的分析发现,对于容量固定的SRAM电路,子存储阵列的划分和子存储单元的行列值划分对于电路性能的影响很大。子存储阵列划分太多,芯片面积会很大,而划分太少则功耗和访问时间就比较大,所以选取合适的电路译码方案非常重要。另外通过低位线摆幅技术改进电路以后,读写功耗降低了30%左右,而采用地址转换侦测技术主要改进了读操作的功耗,降低了40%左右的读功耗,两种技术都大大改进了SRAM电路的性能。更多还原

【Abstract】 All kinds of memory will be embedded in today’s SoC system in order to improve the system’s performance, especially the static random access memory (SRAM). It will be the chief factor when we think about how to select the memory because SRAM is compatible to the standard CMOS process. These memory possess the great proportion of the whole chipset both in the energy consumption and in the chipset area, so the chipset performance is decided by these memory performance. The high performance memory design is most important for SoC system.SRAM circuits need have lower energy consumption, fast access time and little chipset area as soon as possible in SoC system. But by analysis we can see clearly that when we improve one aspect of the circuit performance , the other aspect of the performance will be decreased. So we need to evaluate the change trend of all performance parameter, then we can optimize the design project.Analyzing from the structure of SRAM circuit, we particularly introduce the work state of SRAM’s sub-circuit. By using simulation and analytical based characterization model, we make the SRAM’s energy consumption model, access time model and chipset area model. After this model is applied to the circuit design of ARM720T’s SRAM, we put forward the most optimized design project. At last using this model, we design the Cache which has the 8KB capacity.The 8KB SRAM circuit has been optimized from the circuit structure in this article. We introduce two ways to improve the circuit performance which are lower voltage bitline swing(LVBS) technique and address transition detection(ATD) technique. The LVBS technique is implemented by improving the structure of pre-charge circuit which can decrease the bitline swing of un-hitting memory cell. Then the power consumption will be decreased. ATD technique improve the structure of decode circuit. Using the address transition detection pulse signal, we decrease the open time of wordline and decrease the bitline swing of hitting memory cell.The SRAM which has 8KB capacity is implemented by way of full custom design. The front-end schematic simulation and back-end layout simulation under chart 0.25um process and SMIC 0.18um is passed. Under chart 0.25um process, chipset area of this circuit is 1.92 mm2, access time is 1.8ns, read power consumption is 16.4mW and write power consumption is 13.3mW. Under SMIC 0.18um process, chipset area of this circuit is 1.38 mm2, access time is 1.7ns, read power consumption is 7.5mW and write power consumption is 6.25mW. All of the performance parameter is satisfied by the circuit design. In this article by analyzing the performance model of SRAM circuit, we can find that the partition of the circuit and the sub-circuit is so important for the capacity fixed SRAM circuit. If we divide too many sub-circuit, the chipset area will be larger, otherwise the access time will be longer and energy consumption will be large. So it’s very important to use the proper decoding project. After improving the circuit by LVBS technique, we decrease 30 percent’s energy consumption both of read and write operation. And 40 percent’s energy consumption of read operation is decreased according to ATD technique. Both of the two techniques greatly improved the performance of the SRAM circuit.更多还原