【作者】 王家正；

【导师】 时龙兴；

【作者基本信息】 东南大学 ， 微电子学与固体电子学， 2005， 硕士

【摘要】 近年来,集成电路的性能、规模和复杂度都有了很大的提高,这使得采用系统芯片(SoC)的设计技术逐步取代以功能设计为主的传统设计方法,成为当今超大规模集成电路的发展趋势。随着系统芯片集成更多的功能并采用更先进的工艺,它所面临的高性能与低功耗的矛盾越来越突出。低功耗技术对提高VLSI的可靠性、降低封装成本及提高产品的市场竞争力都有着重要意义,功耗对电路的影响使它成为了集成电路设计中的第三维目标。在自顶向下的VLSI设计过程中,越高层次的设计技术能够达到低功耗的效果越好。本文课题的主要研究方向是系统级低功耗技术。文章首先分析了CMOS电路功耗的产生原因,综述了逻辑综合优化技术、RTL级和系统级低功耗设计方法,并讨论了基于门级仿真功耗估计平台的建立。其次,采用了一种根据各种应用环境动态配置时钟的SoC芯片低功耗管理策略,并在硬件上完成功耗管理(PMC)单元的设计。在操作系统中嵌入了功耗管理程序,采用基于Timeout算法的软件调度策略,预测处理器和模块的空闲状态,控制PMC单元切换工作模式,实现PMC提供的功耗管理功能。芯片实测时通过动态配置时钟频率,从Normal模式转换到Slow模式可以节省88%的功耗;从Normal模式进入Idle模式可以节省21.9%的功耗;从Slow模式进入Idle模式可以节省26.9%的功耗,在Sleep模式下,芯片仅消耗157uW的功耗。在Normal模式下关断MMA、LCDC模块,可以节省10.4%的功耗,而在Slow模式下可以节省12.0%的功耗。在其他工作情况可以根据实际工作需要,关断更多空闲模块节省更多功耗。最后,本文还对动态调整工作电压的低功耗技术进行了研究,其根据电路的实际需要,在不影响处理器性能的前提下动态调整工作电压。完成了动态调压部件中的鉴频器、数字滤波、过电流保护、零电流检测、零电压启动电路的设计,对相应部分进行电路调试和仿真,为动态调压的低功耗设计技术提供了硬件基础。更多还原

【Abstract】 In recent years, the improving performance, augmenting dimension and increasing complexity of the integrated circuit all bring difficulty to the design methods. So that SoC (System on Chip) design relying mainly on function assembly instead of traditional function design becomes the trend and mainstream method of VLSI IC design. With the development of SoC, the conflict between the high performance and low power becomes more and more extraordinary. This adds another degree of freedom and complexity to the design process as well as speed and area.In the Top-Down design flow, the optimization effect on power is better when low-power techniques are used in higher design level. The major research direction of the thesis is system-level power optimization. Firstly, based on the analysis of power resource, the paper summarizes logic synthesis, traditional RTL and system level low power methods, and creates the power estimation flow with EDA tool PowerCompiler. Secondly, a dynamic power management controller (PMC) is adopted which dynamically changes the work modes and clock frequency according to applications. Power management program based on timeout algorithm and event-driven policy is embedded in operation system, which predicts idle period of processor and modules and realizes the function of PMC. By dynamically configurating the clock frequency, the SoC chip saves 88% power from normal mode to slow mode, 21.9% power from normal mode to idle mode, 26.9% power from slow mode to idle mode, and in sleep mode, only consumes 157uW. In normal mode, it can save 10.4% power by closing the MMA and LCDC modules consuming most power, and 12.0% power is saved in slow mode. When more modules are closed in other work enviornment, more power can be saved.Finally, this paper also researches the dynamic voltage scaling mechanism, by making processor work at different but adequate voltages and speeds according to its work load, without sacrificing the system performance. And it completes frequency detector, loop-filter, current limit, zero-current detection and zero-voltage start-up modules, which are debugged and simulated.更多还原