【作者】 姚华；

【导师】 金耀辉；

【作者基本信息】 上海交通大学 ， 通信与信息系统， 2007， 硕士

【摘要】 光分组交换(OPS)技术具有数据速率和格式透明、粒度灵活可调及资源动态分配等优点,成为当前高速宽带数据网的研究热点之一。本文主要研究同步OPS网络边缘节点的设计与实现。本文的研究分为软件和硬件两部分。软件部分主要研究了OPS边缘汇聚节点的组装算法,并提出一种新的更适合同步OPS网络的组装算法;硬件部分介绍了所开发的边缘节点电路板之一以太网收发板。传统的边缘节点组装算法在OPS、OBS等领域已经研究的比较多,然而这些算法都是针对不固定长度组装的特性提出的。同步OPS光分组的特点是长度固定,为了使每个光分组净荷恰好达到额定长度,在组装时必需要填充无用数据,这必然导致网络带宽利用率有所下降。本文根据同步OPS的特点以及网络数据流自相似性的特性,提出了一种新的组装算法:AFL(Adaptive Algorithm for Fixed Length Assembling)算法。AFL算法能在组装延迟较低的情况下,充分提高OPS光分组净荷的有效数据填充率。在硬件方面,本文介绍了硬件开发的两部分工作:以太网收发板开发和FPGA开发。以太网收发板开发主要使用了Intel82545 MAC芯片、PCI9656接口芯片以及Cyclone II FPGA。本板主要负责接收/发送以太网帧、按AFL算法汇聚成/解汇聚光分组。FPGA开发时通过RS232串口与电脑相连进行调试。更多还原

【Abstract】 The Optical Packet Switch (OPS) became one of the most important technical of optical network because of its advantage of great bandwidth and flexibility.The paper contains two parts of research: the software and hardware. The research of software focuses on the assembling algorithm for edge node of synchronous OPS network and a new assembling algorithm is proposed in the paper. The research of hardware is about the development of the Ethernet circuit board for the edge node of synchronous OPS.There is much research on the assembling algorithm in OPS and OBS networks, but all of these algorithms are for the no_length_limit assembling process. The optical packet in the synchronous OPS network is length_limit and in order to make sure each optical packet has the same length, useless data has to be filled into the optical packet, which will reduce the utilization of bandwidth. Based on this character and the self-similar input stream, a new assembling algorithm, AFL (Adaptive Algorithm for Fixed Length Assembling), is proposed in the paper. By adaptively adjusting the parameters for the assembling, AFL algorithm improves the performance of the assembling process, as well as the bandwidth utilization.The research of hardware contains two parts: the design of the circuit board and the development of the program for the FPGA on the circuit board. The circuit board is responsible for transfer/receiving Ethernet frames and assembling/un-assembling optical packets by AFL algorithm. Three main chips are used on the circuit board: Intel82545 MAC, PCI9656, and Cyclone II FPGA. The RS232 interface, which is connected to the PC, is used while debugging the program for the FPGA.更多还原