【作者】 孙伟；

【导师】 胡晨；

【作者基本信息】 东南大学 ， 微电子学与固体电子学， 2006， 硕士

【摘要】 数字电视在我国的广泛应用,对数字电视信号的传输质量有了更高的要求,信道传输质量显得尤为重要,这也就对高效的信道编解码技术提出了更高的要求。Reed-Solomon码是现行DVB-C标准中使用的信道编解码方式,其算法特性和独特的有限域内运算编码的方式使得它在处理连续突发性数据错误上有着十分出色的表现,因而成为欧洲电信标准协会(ETSI)的数字有线传播标准,即DVB-C标准的重要组成部分。文章介绍了RS码依据的迦罗华域基础理论,论述了RS编码及解码原理和相关算法,然后针对HDTV解调芯片中前向纠错部分的RS解码模块,从核心算法的选择出发着重比较四种解码方法,并最终确定了时域内采用Berlekamp算法作为核心算法的解码器设计方案。在设计中采用逻辑简化、分时复用的方法缩小了电路规模,优化了电路结构。整个电路采用Verilog-HDL语言进行描述,各模块及整体电路经ModelSim软件仿真,用SYNOPSYS工具进行逻辑综合,逻辑仿真和FPGA验证表明,RS解码模块在6.875M(byte/秒)的符号率情况下,能实现对RS(204,188)码的解码纠错,符合DVB-C标准,满足QAM解调芯片的要求,并经过了Chartered0.25μmCMOS工艺流片实现。此外,文章最后还提出了对电路进行进一步研究的方向,留待继续研究。更多还原

【Abstract】 Reed-Solomon error correction is a very important technology which exists in today’s digital communication systems. Because of its excellent error correcting ability, Reed-Solomon codes has extensive applications in storage devices, communication and broadcasting, in particular forming part of the specification for the ETSI digital cable television standard, known as DVB-C.Hardware implementations of encoders and decoders for Reed-Solomon error correction require some knowledge of the theory of Galois fields on which they are based. This paper describes the underlying mathematics and the algorithms used for encoding and decoding, with particular emphasis on the choosing of algorithms for key-equation solver (KES) block and their realization in logic circuits. After the analysis and comparison of several representative decoding algorithms, we choose a VLSI solution for our design goal which plays an important role in the FEC block of a new HDTV demodulate chip.Then, we presented all the modules of this RS(204, 188) decoder which is fully compatible with the DVB-C standard, and using time-division-multiplex(TDM) which is the main idea of several methods to optimize the architecture and minish circle scale. After optimization the circuit not only meets the performance requirement of the HDTV receiver chip but also have smaller circuit scale, complexity and lower cost. Through the whole process of Verilog-HDL coding, RTL simulation and synthesis, the proposed RS decoder has been implemented with the Chartered 0.25μm CMOS standard cell technology. The result shows that the design can be used for RS(204,188) at the speed of 6.875MHz. At the end of the paper, relative simulation and test results together with the parameter of the decoder are provided. Worked examples are provided to illustrate the processes involved.更多还原