【作者】 陈晓斌；

【导师】 汪辉；

【作者基本信息】 上海交通大学 ， 软件工程， 2006， 硕士

【摘要】 静电放电对微电子器件的危害越来越受到人们的重视。本文简介了静电的产生和抑制,介绍了人体模型、机器模型和带电器件模型及其模拟测试方法,以及静电放电保护电路,利用实验的方法重点研究了三种静电放电模型的失效特征。这一研究有助于人们在失效分析时能够识别静电放电的类型,从而更有效地帮助调查静电放电的根源。静电放电会影响微电子器件的生产成品率、制造成本、产品质量和可靠性。尽管在过去的十多年中,科技工作者为降低静电的危害已作了很多努力,但是随着集成电路特征尺寸的减小,静电放电对微电子器件的危害却越来越严重。本课题通过对人体模型、机器模型和带电器件模型的理论认识,设计实验方案和研究实验结果,再结合实际工作中遇到的许多静电失效案例的研究,区分出三种模型所引起的器件失效,从而更有效地帮助调查静电放电的根源,不断改进静电防护措施,降低静电所造成的损失,保证产品可靠性。本研究课题的依据在于:1.不同静电放电模型的放电时间不同,造成器件损伤的能量不同。相比之下,电过应力造成的损伤比静电放电造成的损伤更严重。失效分析时,通过对失效部位的光学和扫描电子显微镜的目检,判断器件损伤的严重程度,作为区别电过应力(EOS)和静电失效(ESD)失效的判据之一。2.三种静电放电模型的放电波形不同,造成器件损伤的位置不同。利用光发射显微镜或液晶热点分析等技术进行缺陷定位,利用反应离子刻蚀机(RIE)和湿法腐蚀对器件进行逐层剥离分析,可确定损伤的位置。3.集成电路的引出脚可分为电源脚、接地脚、信号输入和输出脚。不同类型的引出脚,会使用不同结构的静电放电保护电路。它们对不同类型的静电放电模型的响应不同,导致器件损伤的部位不同。通过对失效器件的电性能测量,结合观察到的缺陷位置,以及静电放电保护结构更多还原

【Abstract】 Electrostatic discharge (ESD) damage to IC(Integrated Circuit) has been paid more attention than ever. This paper introduces generation of static electricity, three kinds of ESD models and test methods, and ESD protection circuit. ESD failure mode, failure mechanism, experiment plan and results, and failure signature of the three ESD models are discussed. This work will help for identifying ESD failure model and for finding ESD source in failure analysis.While obvious Electrical Over-Stress may be physically evidenced by cracked packages, carbonized mold compound, burnt-out bond wires and massive visual damage to the metal on the die surface. The more subtle ESD failure is not visible at low magnification. However in most instances, the observation of discoloration will provide a means of differentiating between the EOS and the ESD events.Failure signatures between HBM (Human Body Model) and MM (Machine Model) show some variation in morphology but they are located in the same ESD protective structure. In all cases no physical anomaly was observed after decapsulation. Scanning electronic microscope examination was required in conjunction with deprocessing to establish physical failure site morphology and final location of the physical damage. Due to the much lower threshold voltage required for electrical failure and higher peak of discharge current, the damages for MM are more severe.The physical failures for CDM (Charged Device Model) occur at the input buffer circuit with gate oxide damage or poly-silicon damage, located in core circuitry not in peripheral circuitry of the die. This location is beyond更多还原