【作者】 况敬波；

【导师】 马光胜；

【作者基本信息】 哈尔滨工程大学 ， 计算机应用技术， 2006， 硕士

【摘要】 随着数字通信和电子商务的不断发展，人们对信息安全的要求越来越强烈。为了保证信息的安全，人们发展了各种各样的密码体系来防止信息被窃取和篡改。公钥密码算法，例如RSA、ECC和DSA等在现代保密体系里占据着非常重要的地位。 RSA算法是最具有典型意义的公钥加密算法，目前大多数采用公钥密码进行加密和数字签名的产品和标准使用的都是RSA算法。RSA算法的安全性是基于大整数素因子分解的困难性，而大整数因子分解问题是数学上长期的难题，至今没有有效的方法予以解决，因此RSA算法是公认安全度比较高的算法。RSA密码算法需要进行大操作数的模指运算，目前公认的模长为512～2048二进制位，运算强度非常大，用软件方法实现会非常慢，因此我们采用适合VLSI实现的Montgomery算法设计RSA算法IP。 本文首先介绍了RSA算法以及Montgomery模乘算法，在此基础上中提出两种改进方案。其中，采用4-2保留进位加法器的改进Montgomery算法可以消除大整数加法运算的进位传播，降低电路的关键路径延时，同时避免了中间数据的类型转化，节约运算时间。另外，使用心动阵列结构将该算法进行影射，消除了全局数据和控制信号广播，使得信号只在相临的两个处理单元中传送，减少互连延时，非常适合超深亚微米技术。同时，对每一个CSA单元在布尔函数级的进行重新调度，使得关键路径延时减少36％。 最后，采用自顶向下的设计方法对RSA加密模块进行划分，并使用Verilog HDL完成了RSA软IP核的描述，并对该软核进行了仿真，仿真结果正确。更多还原

【Abstract】 As the development of digital communication and e-business, People’s requirement of information security is getting stronger. People develop various crypto-systems to prevent the information from being stolen and illegally modified. Public-key cryptography algorithm such as RSA, ECC and DSA plays an very important role in modern crypto-system.RSA algorithm is the most typical public-key cryptography algorithm. Nowadays RSA is used in most encryption and digital signature product and standard, its security is based on the difficulty of the factorization of large integer. People have not yet found an efficient method to solve the integer factorization problem. So RSA is believed to be a secure algorithm. Since the modular exponentiation operation which has a modular of 512 to 1024 bits will causes a heavy load of general purpose CPU, the software implemented RSA algorithm will be very slow. To be fast, we propose a VLSI implemented RSA algorithm accelerator IP using Montgomery algorithm.The RSA algorithm and Montgomery algorithm are introduced first. Then two modified methods are proposed. The 4-2 CSA based Montgomery algorithm can eliminate the carry propagation of large integer addition. It has a low crucial path delay and avoids the conversion of temporary variables. The algorithm is projected to the systolic array which eliminates the global broadcast of data and control. The signals are transferred only in the adjacent processing units. The systolic array increases the processing parallelism and is very suit for the design of VDSM. The CSA unit is rearranged at the Boolean level. It decreases the crucial delay by 36%. The function definition and structure partition are finished with the top-down design method. The soft core of RSA algorithm is depicted with Verilog HDL and the behavior simulation is achieved.更多还原