LDPC测试平台时域同步算法设计及FPGA实现

【作者】 毛磊；

【导师】 于鸿洋；

【作者基本信息】 电子科技大学 ， 信号与信息处理， 2006， 硕士

【摘要】 中国地面数字电视广播融合方案是根据中国数字电视发展现状提出的一套地面数字电视标准,其中使用LDPC码作为前向纠错编码。由于软件仿真的诸多局限,所以本课题通过搭建硬件测试平台,完成LDPC码的解码-误码测试工作。测试平台中的时域同步是OFDM系统下基于PN序列的符号和频率同步,其算法是根据融合方案时域同步算法,同时结合测试平台系统要求设计的,算法性能已经通过Matlab仿真得以验证。目前时域同步的Verilog模块设计已经完成,并且通过了FPGA片上调试,达到预期效果。本文将首先概述数字电视的发展现状和中国地面数字电视融合方案及测试平台。介于本人在该项目中的主要工作是时域同步算法设计及FPGA实现和LDPC码译码器的FPGA设计,在文章的第三章将系统的介绍测试平台时域同步的算法设计过程及Matlab仿真分析,第四章将介绍时域同步的FPGA设计、仿真及硬件调试。第五章为文章的总结部分。LDPC码译码器的设计不是文章重点,所以只在第二章结尾部分作简要的介绍。在本人的研究生学习阶段主要参与了这个项目中的工作,主要内容可以概括为以下几点:1.根据融合方案同步算法设计测试平台时域同步算法,并编写Matlab程序进行仿真验证。2.根据Matlab程序编写Verilog模块,完成功能仿真和时序仿真。3.在硬件平台上对同步模块进行调试,达到预期目的。4.根据算法进行LDPC码解码器的FPGA设计。更多还原

【Abstract】 The merged blue print for digital terrestrial television broadcasting which suits to the developing status of DTV in China is a standard of the Chinese DTV-T. LDPC code is used as FEC. The narrowband LDPC code platform is constructed to test the ratio error of the LDPC decoder, for the restriction of the software debugging.Usually in OFDM system, the time-domain synchronization in the platform is the symbol-frequency synchronization using PN-sequence preambles. Its algorithm has been designed based on the requirement of platform, and validated by Matlab simulation. Then the Verilog program has been designed based on this algorithm. Finally, the hardware Debugging has been done.In this thesis, the developing status of DTV is introduced firstly. The merged blue print for digital terrestrial television broadcasting in China and the structure of platform is introduced following. In the project of constructing the platform, the design of the time-domian synchronization algorithm is in the charge of me, which has been realized on FPGA. It is introduced detailedly in chapter 3 and chapter 4. Additionally, the design of LDPC decoder based on FPGA is another part of the project. It is introduced briefly in the end of chapter 2. This thesis is summared in Chapter 5. The main work described in this project is listed as follows:1. Design the time-domain synchronization algorithm of platform, and simulate it in Matlab.2. Design the Verilog program and finish all kinds of simulation.3. Debug the Verilog program on the hardware platform.4. Design LDPC-decoder based on FPGA.更多还原