节点文献

基于Nios II软核CPU嵌入式消息转发系统的设计与实现

Design and Realization of Embedded Information Transmiting System Based on Nios II Soft CPU

【作者】 唐如鸿

【导师】 李成忠;

【作者基本信息】 西南交通大学 , 计算机应用技术, 2006, 硕士

【摘要】 论文紧跟嵌入式系统发展趋势,采用一种新的嵌入式系统设计技术——SOPC(片上可编程系统)技术进行通信产品开发。Nios嵌入式处理器是Altera公司推出的一个32/16位精简指令处理器软核,能够在可编程逻辑器件上完成SOPC设计。 论文分析了NiosⅡ处理器的结构、性能及总线特性。Nios Ⅱ是Altera公司的最新的SOPC技术,它是一个32位精简指令处理器软核,专门为SOPC设计的一种CPU,它以IP核的形式提供给嵌入式设计者。它的可配置特性给嵌入式系统设计带来了更大的灵活性,为嵌入式系统的设计提供了一种全新的思路。能够在可编程逻辑器件上完成SOPC设计。通过将32位高性能处理器在内的多种应用模块嵌入到一个通用的FPGA内,实现了一个完全可重置的嵌入式系统。 论文对Nios Ⅱ在通信领域的应用进行研究和验证。将Nios Ⅱ软核应用在通信产品主控板上,作为主CPU的协处理器,分担主CPU的业务功能。在Stratix Ⅱ FPGA芯片内,实现一个Nios Ⅱ软核用于主控板与业务板的通信管理。 最后,对系统进行了测试和验证,分析了测试结果,验证了本系统方案设计的正确性和基于Nios处理器实现可编程片上系统的可行性。尝试用新的SOPC技术,在软、硬件开发过程中,缩短设计开发周期,达到应用功能的快速实现,节约开发成本,优化性能和资源。成功地实现和验证了Nios软核处理器对大流量通信信息处理,并在公司推广了Nios软核处理器的应用与研究。

【Abstract】 The thesis follows on the heels of trend of embedded system designtechnology, Introduces a new technology of embedded system design-SOPCtechnology, and applying it to research of communications. Nios embedded processor is a 32/16-bit RISC processor soft core developed by Altera that facilitates SOPC design on FPGA.The thesis analyses the Nios II processor soft core, including structure of system , performance of working and characteristic of Avalon bus .the Nios II processor soft core is the latest technology of SOPC. Nios II is a 32-bit RISC processor soft core;Nios is a kind of CPU that designed for SOPC specially. For embedded system designer, it’s a kind of IP core. Nios has the characteristic of reconfiguration, which brings more flexibility to the designer. Nios has offered a kind of brand-new train to Embedded System designer. It can accomplish the SOPC design based of FPGA. It realized a reconfiguring embedded system by embedded the Nios soft core and others application IP discreteness in FPGA.The thesis research and realize the application of communications. Apply Nios II soft core in the master board , As a coprocessor, partaking functions of the main CPU. using one piece of Stratix II FPGA chip to realize the function of the communications management of main board and sub board.At the end of the thesis, the system design is realized and validated successfully in this thesis by the result of testing, try the new SOPC technology.in development of software and hard design, It is used as a coprocessor of main CPU to realize the system level functions, alleviating the use of peripheral parts and accelerating the realization of application functions. It shortens the design period, saves upgrade cost and optimizes performance and resources.

【关键词】 嵌入式系统BootloaderSOPCNios IIUC/OS IIFPGAUART
【Key words】 embedded systemBootloaderSOPCNios IIUC/OS IIFPGAUART
  • 【分类号】TP311.52
  • 【被引频次】11
  • 【下载频次】621
节点文献中: 

本文链接的文献网络图示:

本文的引文网络