【作者】 程松林；

【导师】 周祖德；

【作者基本信息】 武汉理工大学 ， 通信与信息系统， 2006， 硕士

【摘要】 随着大规模集成电路和计算机技术的飞速发展,数字技术渗透到各个技术领域。但是自然界中大多数物理信号却是模拟信号,因此,将模拟信号转化成数字信号是进行信号处理和分析的首要前提。数据采集系统即是完成将模拟信号转换成计算机能识别的数字信号的任务。 传统的数据采集系统是基于ISA总线设计的,由于ISA总线带宽的限制,无法满足高速数据传输的要求。而PCI局部总线的引入,打破了数据传输的瓶颈,它以其优异的性能成为微机总线的主流。基于PCI总线的数据采集系统是高速数据采集的发展方向。传统数据采集卡一般使用SRAM或SDRAM作为数据缓存,SRAM容量小,价格昂贵,SDRAM价格便宜,但数据传输带宽有限,本文采用DDR SDRAM作为缓存,存取速率高,存储容量大,且价格便宜。 本文从硬件设计和驱动程序开发两个方面对基于PCI总线的高速数据采集卡进行了研究。论文中首先讨论了DDR SDRAM的特性,DDR控制器的基本结构和时序,以及PCI总线的基本结构和时序,并介绍了FPGA的基本原理和开发过程。然后对基于PCI总线的高速数据采集卡的各模块进行了详细的设计,包括AD转换接口设计,DDR控制器设计和PCI总线控制器模块设计。文中采用FPGA实现了DDR控制器功能和PCI总线控制器功能。外加DDR存储器作为高速缓存是提高数据采集卡采样速率的一个重要措施,AD转换芯片的数据通过DDR控制器存入DDR SDRAM,DDR SDRAM中的数据再通过PCI总线传给上位机处理,完成了对信号的采样、数据的存储和传输功能。论文给出了用FPGA进行时序逻辑设计的基本原理图和Verilog程序。最后还介绍了对PCI总线数据采集卡驱动程序WDM的开发及编程方法。 通过仿真和测试,该数据采集卡采样率可达到250MSPS,存储容量可达1GByte。更多还原

【Abstract】 With the rapid development of LSI (Large Scale Integration) and computer science, digital technology has penetrated into every field of knowledge. As most physical signals in the nature are analog signals, the conversion from analog signals to digital signals has become the key step in the process of signal processing and analysis control. Data acquisition system converts analog signals to digital signals, which can be recognized by computer.Traditional data acquisition system is designed based on ISA bus, but with the limits of its bandwidth, it is difficult to perform high-speed data transmission. PCI local bus, with its outstanding capability and excellent adaptation, has resolved this problem and become the main bus in the computer. PCI bus-based data acquisition system has played a dominant role in high-speed data acquisition. Meanwhile, traditional data acquisition board uses SRAM or SDRAM as data buffer. As SRAM has low capacity and high cost, while SDRAM has low cost and limited transmission bandwidth, DDR SDRAM is adopted as data buffer in this paper, which has merit of high speed, high capacity and low cost.PCI bus-based high-speed data acquisition board, including hardware design and driver program, is researched in this paper. Features of DDR SDRAM, basic configuration and timing of DDR controller, together with basic configuration and timing of PCI bus, are discussed first, while basic theory and development process of FPGA are introduced. Then each module on PCI bus-based high-speed data acquisition board is detailed designed. FPGA is adopted to realize functions of DDR controller and PCI bus controller in this paper. The accession of DDR controller as data buffer is an effective measure to enhance the sampling frequency of data acquisition. Data after A/D conversion will be stored in DDR SDRAM through DDR controller, and then the stored data will be transmitted by PCI bus to upper computer for processing. The whole board realizes functions of signal sampling, data storage and data transmission. The schematics and Verilog source program of timing logical design using FPGA are presented in the paper. At the end of the paper, development of driver program WDM for PCI bus-based data acquisition board is mentioned.Through simulation test, the sampling frequency of the board can reach 250 MSPS, while storage capacity can achieve 1 GByte.更多还原