【作者】 曹李秋；

【导师】 聂明新；

【作者基本信息】 武汉理工大学 ， 通信与信息系统， 2006， 硕士

【摘要】 软件无线电是当前军事与移动通信领域的研究热点之一,由于受A/D/A和DSP芯片处理速度的限制,目前的软件无线电系统大多采用折中的实现方案,就是增加专用的数字下变频器或者运行数字变频算法,改变中频或射频信号的采样频率,以保证通用DSP芯片进行实时信号处理。 数字下变频的主要目的是经过数字混频将A/D转换输出中频信号搬移至基带,然后通过抽取,滤波完成信道提取的任务。由于软件无线电具有宽带、开放、可编程等基本特点,这就要求变频部分的数控本振必须能产生分辨率高的数字样本来负责载波通道选择;要求抽取滤波器有可编程性及良好的抗混叠特性,以达到窄带和宽带信号的提取;要求脉冲成型滤波器具有良好的信道整形特性并且具有可编程性。FPGA高效的算法结构和可重构性为软件无线电数字中频下变频处理提供了良好的条件。 本文就是针对软件无线电的数字变频技术展开研究。讨论了基于宽带中频带通采样软件无线电接收机模型的中频数字化的理论,研究了数字下变频的实现结构,在此结构基础上,首先运用数字频率直接合成思想设计了数控振荡器(NCO),数控振荡器采用只读存储器查表方法实现,具有灵活、易于实现、频率分辨率高等特点;数字下变频需要高效的抽取滤波器,本文讨论了多速率信号处理理论,主要研究了用于降速处理的抽取理论,并深入研究了一种高效的滤波器——级联积分梳状(CIC)滤波器,CIC滤波器作为抽取滤波器实现可编程抽取,CIC滤波器不需要乘法器,不需要存储滤波器系数,仅使用延时和加法操作,因而很适合采用FPGA实现;在数字下变频的多级高效数字滤波器模块中,最后一级一般要使用FIR整形滤波器对整个信道进行整形,尽可能让期望信号通过,同时尽可能抑制无用信号。基于FPGA的分布式算法能够高效实现FIR数字滤波的乘累加(MAC)运算。本文对分布式算术算法进行了深入研究,运用ROM分解技术、偏移二进制编码(OBC)以及线性相位FIR滤波器的对称结构使得ROM规模减小,实现了串行分布式算法结构的改进。更多还原

【Abstract】 Software radio is one of the hotspots in radio communication and military research. Due to the poor processing speed of A/D/A conversion and DSP processor, software radio often adopts inter-specific schemes based on digital conversion technology. That is to say, by using specific DDC and DUC or running relevant algorithm, software radio transforms the sampling rate to enable DSP processors bring real-time signal processing to success.A Digital Down Converter(DDC) converts an intermediate frequency(IF) band signal into a baseband signal by using a mixer in the digital region and a low-pass decimation filter which can extract one signal channel from the received after the analog-to-digital conversion. Because software radio is broad-band, open, and programmable, it requires high resolution Numerical Controlled Local Oscillator which allows carrier channels to be selected from a wide frequency band, and ,it requires high efficient programmable decimation filters with good anti-aliasing feature which can extract both desired narrow band and wideband signals, it also requires programmable Finite Impulse Response(FIR) filters to reject the out of band signal. Field Programmable Gate Array (FPGA) has efficient algorithm structure and reconfigurable feature, which can support the digital IF processing well.In this thesis, signal processing of DDC is investigated, and the implementation of some key components in DDC is focused on. In the first place, the thesis presents the theory of IF signal processing based on a generic software radio configuration and the mechanism in DDC. Then an Numerical Controlled Oscillator using ROM Look-Up-Table(LUT) technology was designed, which has flexibility and high resolution. Since efficient decimation filters is very important for DDC, Cascaded Integrator Comb(CIC) Filter is concerned. CIC filter has simple structure without coefficients, it carries filtering through delay units and adders, which is suitable for FPGA implementation. In the thesis, a CIC filter with programmable decimation rate was designed. In the blocks of efficient filters of DDC, FIR plays a key role inrejecting the unwanted signals. Distributed Arithmetic(DA) as an important technology has been proved efficient in implementing Multiply-Accumulator(MAC). In this thesis, ROM decomposition technology, offset-binary coding technology and symmetric architecture were used to improve the Serial Distributed Arithmetic FIR structure by ROM size reduction.更多还原