【作者】 胡晓宇；

【导师】 邹雪城；

【作者基本信息】 华中科技大学 ， 微电子学与固体电子学， 2005， 硕士

【摘要】 随着集成电路工艺复杂度和设计复杂度的提高,集成电路的测试成本在总的设计成本中所占的比例正逐年攀升,集成电路的测试变得越来越困难,传统的自动测试设备(ATE)已经不能满足集成电路测试的需求,可测性设计已经成为了解决芯片测试问题的主要手段。可测性设计技术目前是VLSI 设计中的热点,它通过增加一些额外的电路来提高电路的可测性以降低测试的复杂性。本文以STN LCD 驱动控制芯片的设计为实例,对目前主流的各种可测性技术进行了比较分析,形成了自己的结构化测试方案。本芯片的嵌入式SRAM 采用内建自测试的解决方案,通过对面向bit 读写的March 算法的改进形成了适合检测本项目的March 算法,此算法可以有效的检测出SRAM 中存在的固定型故障、跳变故障、地址译码故障、读写开路故障及耦合故障。根据本设计内嵌SRAM的结构特点,在MBIST电路结构上采取并行测试方式,有效地节约了MBIST给芯片带来的硬件开销。本设计的核心逻辑部分采用基于Stuck-at 故障的全扫描测试方案,选取多选触发器扫描模式替换时序单元,完成扫描链的插入,使用DFT CompilerTM 构造3 条扫描链,通过增加少许电路结构,解决了影响电路可测性的多个问题有效的提高了测试覆盖率。使用TetraMAXTM完成自动测试图形生成(ATPG),通过对错误仿真分析表明,扫描测试达到了较高的测试覆盖率。本设计的可测性设计共增加电路面积约4%,端口增加了11 个。从总的实现结果来看这套解决方案完全满足代工厂的流片测试要求,达到了预期的目标。更多还原

【Abstract】 As the complexity of Integrated Circuit design and process is improving, the cost of test and its ratio in the total NRE of IC design are both rising greatly and the IC’s test is becoming more and more difficult. The conventional Automatic Test Equipment (ATE) can not satisfy the requirement of Integrated Circuit’s test. Design for testability (DFT) technology has become the main method to resolve the issue of chip test. Design for testability techniques offer one approach toward enhance testability by adding enough extra circuitry to a circuit or chip to reduce the complexity of testing. Because the cost of hardware is rising as the cost of testing decreases, there is now a growing interest in these techniques for VLSI circuits. Our project is a 4-gray scale STN LCD driver and controller. We compare the mainstream DFT technology in performance aspect and bring forward our structured DFT strategy. Full-scan testing for core logic and MBIST for embedded memory are adopted for the chip testing. The ameliorated March test algorithm which is sourced from bit-oriented March test algorithm insure 100% fault coverage for stuck -at fault、stuck -open fault、transition fault、address decoder fault. Through adding a very small number of circuits the testability problem was removed. Three scan chains of multiplexed flip-flop style be constructed to achieve a SAF(stuck-at fault) in the chip, and the test pattern was generated in TetraMAX. High test coverage is achieved through ATPG faults simulation. The cost of DFT is adding 4 percent area and 11 pins. In a conclusion the structured DFT of the chip shows a good result to meet production manufacturing requirements.更多还原