【作者】 邓丽娟；

【导师】 田金文；

【作者基本信息】 华中科技大学 ， 模式识别与智能系统， 2005， 硕士

【摘要】 随着移动终端、多媒体、Internet 网络、通信,图像扫描技术的发展,以及人们对图象分辨率,质量要求的不断提高,用软件压缩难以达到实时性要求,而且会带来因传输大量原始图象数据带来的带宽要求,因此采用硬件实现图象压缩已成为一种必然趋势。而熵编码单元作为图像变换,量化后的处理环节,是图像压缩中必不可少的部分。研究熵编解码器的硬件实现,具有广阔的应用背景。本文以星载视频图像压缩的硬件实现项目为背景,对熵编码器和解码器的硬件实现进行探讨,给出了并行熵编码和解码器的实现方案。熵编解码器中的难点是huffman编解码器的实现。在设计并行huffman 编码方案时通过改善Huffman 编码器中变长码流向定长码流转换时的控制逻辑,避免了因数据处理不及时造成数据丢失的可能性,从而保证了编码的正确性。而在实现并行的huffman 解码器时,解码算法充分利用了规则化码书带来的码字的单调性,及在特定长度码字集内码字变化的连续性,将并行解码由模式匹配转换为算术运算,提高了存储器的利用率、系统的解码效率和速度。在实现并行huffman 编码的基础上,结合针对DC 子带的预测编码,针对直流子带的游程编码,能够对图像压缩系统中经过DWT 变换,量化,扫描后的数据进行正确的编码。同时,在并行huffman 解码基础上的熵解码器也可以解码出正确的数据提供给解码系统的后续反量化模块,进一步处理。在本文介绍的设计方案中,按照自顶向下的设计方法,对星载图像压缩系统中的熵编解码器进行分析,进而进行逻辑功能分割及模块划分,然后分别实现各子模块,并最终完成整个系统。在设计过程中,用高级硬件描述语言verilog HDL 进行RTL 级描述。利用了Altera 公司的Quartus II 开发平台进行设计输入、编译、仿真,同时还采用modelsim 仿真工具和symplicity 的综合工具,验证了设计的正确性。通过系统波形仿真和下板验证熵编码器最高频率可以达到127M,在62.5M 的情况下工作正常。而熵解码器也可正常工作在62.5M,吞吐量可达到2500Mbps,也能满足性能要求。仿真验证的结果表明:设计能够满足性能要求,并具有一定的使用价值。更多还原

【Abstract】 With the development of teconologies of mobile ,multimedia,internet,communication,and image scaning teconogies,and also the higher and higher requirement for the resolution &quanlity of image,it’s hard to meet the real-time requirement of image & vedio copression sysytems by software.So it is to urged to implement compression system by hardware.And In most of the image compression systems,there are entropy encoder following the transformation unit and the quantitier.So Hardware design of parallel Entrpy codes can be wildly used in real-time image compression &vedio compression systems. In this assay, we explore the design of parallel Entrpy codes with “the Satellite video compression”as the background, and the hardware implementation of Entrpy codes is provided. The design of Huffman encoder and decoder are the key parts of the codes. In the design of parallel huffman encoder,we improved the control logic of the packing unit to avoid the error coursed by data missing.And in the design of parallel huffman decoder ,we make full use of the monotony and continuity of the regulated Huffman code ,transforming the parttern mating of decoding to arithmetic opration ,highly decrease the number of memory unit and increasing efficiency and speed of decoding process. The Huffman encoder is linked with the DPCM (processing data of DC sub-band) and run-length encoder (processing data of AC sub-band) to compress the data output by quantitizer after DWT .And The Huffman decoder is linked with the DPCM decoder (processing data of DC sub-band) and run-length decoder (processing data of AC sub-band) to decompress the compressed data and output to quantitier, then to I DWT unit to get back the image. The design of system of RTL Level is discripted by verilog HDL in the top-down way. According to the STA of Quartus II, f max of the entropy encoder is 127M, and timing simulation implies that it work right at the clock 62.5M. And entropy encoder can work right at the clock 62.5M, with the throughout of 2500Mbps. After simulation, complying, mapping and routing, the design is downloaded to the FPGA chip, it also works right and get the right result. Simulation & FPGA validation imply that the design can meet the functional and timing requirent of the project.更多还原