【作者】 樊华；

【导师】 冯全源；

【作者基本信息】 西南交通大学 ， 计算机应用， 2005， 硕士

【摘要】 近几年来,从一些世界性的仪器仪表展览会及各大公司争相推出“低功耗”、“微功耗”以至“零功耗”产品可看出,低功耗设计已经成为电子产品设计的主流。作为电子产品中必不可少的器件之一的电源管理器件与整个电子产品的发展休戚相关。目前,电源管理集成电路市场大部分被国外产品占据,研究开发国内的电源管理电路产品,能夺回巨大的市场。因此,开展本项目的研究具有特别重要的意义。在国家自然科学基金和四川省学术带头人基金的资助下我们对电源管理芯片进行了研究。 本论文设计了一种基于LDO线性电压变换器的超低功耗放大器,该LDO线性电压变换器一般应用于移动电话与无线通信设备、PDA、数码相机、携带型电池设备等。放大器采用0.6um BiCMOS工艺进行设计。此放大器的突出优点是与过流保护电路融合在一起,使得芯片不需要专门的限流模块,大大减少了器件与电流支路,极大地提高了电流利用率,实现超低功耗。 我们通过对误差放大器的原理分析,提出了符合实际的电路数据,借助于仿真设计软件HSPICE对电路进行了完整的设计并对误差放大器的共模输入范围CMR、差模输入范围、开环增益、电源抑制比PSRR、共模抑制比CMRR等进行了模拟仿真,结果表明该误差放大器电路的电特性参数均达到芯片的设计指标。 本论文首先简要地介绍了电源管理芯片的重要性、分类以及国内外发展现状,面临的问题;接着叙述了MOS模拟集成电路基础;最后,提出了一种新型的基于LDO线性电压变换器的超低功耗误差放大器,然后列出了一个较新的LDO误差放大器电路及HSPICE仿真波形与本文设计的误差放大器进行比较,最后详细讲述了本文设计的误差放大器的各项性能指标的HSPICE仿真结果,结果表明,本文所设计的误差放大器静态电流约0.6uA,实现了超低功耗。更多还原

【Abstract】 Due to the advances in the fabrication process field of integrated circuits, the component density and the overall power dissipation of the high performance VLSI chips increase continuously. In particular, the explosive proliferation of battery-powered equipment in the past decade has accelerated the development of low-power-consumption low-dropout (LDO) voltage regulators, which has intensified the focus of designers on optimizing the performance of the amplifiers. Nowadays, foreign enterprises almost occupy the whole market of power management IC, so it is necessary to dominate such a potential market. Therefore, it is of great significance to research and develop domestic power management. Moreover, it is of great importance to study the LDO linear regulator circuit. Supported by National Science Foundation of China and Sichuan Province Academic and Ttechnologic Leaders Foundation, we have held deep research in power management chip. The typical application of the chip includes the Mobile phones, Wireless communication equipment, PDA, portable equipment, Battery powered equipment. In this paper, an error Amplifier applied to a low dropout (LDO) linear voltage regulator has been designed. The chip is manufactured by BiCMOS process. Moreover, this amplifier reaps the benefit of incorporating foldback current limiting circuit, which enables the Low-Dropout (LDO) voltage regulator without the need of special current limiting subblock, therefore, the object of ultra-low power is realized because of great reduction in transistors and current limbs.In the first part, this paper introduces the background and significance of this research. In the second chapter, single stage amplifiers are narrated. After that, on the basis of the prior knowledge, we have successfully design an error amplifier. HSPICE simulation results which includes CMR (common mode input range), differential mode input range, Power Supply Rejection Ration (PSRR), common mode Rejection Ratio (CMRR) and so have shown that the amplifier only consumes about 0.6uA quiescent current.更多还原