【作者】 赵莹；

【导师】 吴丽华；

【作者基本信息】 哈尔滨理工大学 ， 计算机应用技术， 2005， 硕士

【摘要】 数字集成电路是当今发展最快的技术领域之一,随着数字电路设计及工艺技术的发展,电路的规模和复杂度日益增大,使得电路的测试生成日益困难,并已成为集成电路芯片生产的瓶颈。对于复杂的大规模集成电路,传统的测试生成算法已不再适用,因此研究新型有效的数字集成电路测试生成算法具有十分重要的理论价值和实际意义。集成电路的测试生成问题是数学上公认的难题—NP 完全问题,在过去的几年中,国内外的学者虽然提出了许多新的测试生成算法,但是到目前为止还没有一种算法能适合所有的大规模集成电路,集成电路的测试生成问题已成为一个重要的研究课题。本文采用单固定故障模型和路径时滞故障模型,对数字集成电路的测试生成进行研究,为提高故障覆盖率,减小测试生成时间,重点研究了以下内容: 1.综述了集成电路测试生成技术的研究现状和发展概况,指出了目前存在的问题和不足之处,并且展望了未来的发展趋势。2.研究了基于二值Hopfield 神经网络的组合电路测试生成算法。并在此基础上,将三值神经网络应用于组合电路测试生成算法中,用三值神经网络表示数字电路,可以减小搜索空间,避免很多不必要的赋值,因此可以在保证具有较高故障覆盖率的情况下,减小测试生成时间,提高算法的测试生成效率。通过构造电路的约束网络,求解约束网络对应能量函数的最小值点得到故障的测试矢量。　　　　　3.研究了基于布尔差分的组合电路测试生成算法。针对布尔差分法存在大量异或运算的问题,提出了组合电路单固定故障测试生成中求解一阶布尔差分的简化方法,它不用异或运算,而是通过求解恒等式来得到完全测试集,避免了大量的布尔运算。同时,通过对二阶布尔差分的剖析,得到了二阶布尔差分法的简化算法,为双故障的测试生成提供了方便。4.　研究了组合电路中非鲁棒性路径时滞故障的测试生成算法。时滞故障是集成电路故障中的一种,电路中如果存在时滞故障,将导致它在给定的高速时钟频率下无法正常工作。因此研究时滞故障的测试生成算法非常重要。迄今为止,国内外学者提出了很多时滞故障模型,其中路径时滞故障模型是最常用的。更多还原

【Abstract】 Digital integrated circuit is one of the quickest techniques in development. With the development of the design for the digital integrated circuits and the technique of craft, the scale and the complexity of the digital integrated circuits become more and more large, and the test generation for the digital integrated circuits is becoming increasingly difficult. It has become the bottleneck for the production of integrated chip. The traditional test generation algorithm is inefficient for the VLSI circuits. So the research of new and effective test generation algorithms has very important value and meaning. The problem of test generation for the digital integrated circuits is a hard solved problem in mathematics ,because it is a NP-completeness problem, which has been proved. Although many test generation algorithms have been proposed in the last few years, there is no one that is efficient for all VLSI circuits. The problem of test generation for the digital integrated circuits has become an important research subject. The test generation for the digital integrated circuits is selected as research target in this paper. The single stuck-at fault model and the path delay fault model are used. It mainly aims to improve the fault coverage and reduce the test generation time. The main contents are as following: 1.　The development and current research status of the test generation for the digital integrated circuits is introduced in this paper. The existing problems and future direction for development are pointed out. 2.　The test generation algorithm based on Hopfield neural networks for combinational circuits is studied, three-valued neural networks is applied in the test generation and the test generation algorithm based on three-valued neural networks for combinational circuits is proposed in the paper. Representing digital circuits by three-valued neural networks may reduce research space and avoid many wasteful assignments. So three-valued neural networks’application in combinational test generation may reduce test time and improve test efficiency. The test vectors for fault can been obtained by constructing the constraint network of the circuits and solving the minimum of energy function of the constraint network. 3.　The test generation algorithm based on Boolean difference for combinational circuits is studied. Considering that there is a lot of exclusive OR calculation in the Boolean difference, a simplified method that solves first order Boolean difference in the course of generating test vectors for single stuck-at fault in combinational circuit is proposed. In this method, test vectors for combinational circuit can be obtained only by solving an identity and exclusive OR calculation is not needed. The simplified method of second order Boolean difference is obtained by analyzing the second order Boolean difference, and it provides convenience for the test generation of two faults in the combinational circuit. 4.　The test generation algorithm for non-robust path delay fault in combinational circuits is studied. There are many faults in digital integrated circuit, one of which is delay fault. The circuit can’t work properly at high-speed clock frequency if there is delay fault in the circuit. So it is very important to study the test generation for delay fault. Until mow, many delay fault models have been proposed by scientists, the path delay fault model is one of the most general models among them. However, the disadvantage with the path delay fault model is that the number of faults with respect to the number of gates in the circuit is exponential, and generating test vectors for faults in short time is generally hard. We will generate test vectors for non-robust path delay fault using stuck-at fault test generation algorithm by using path-leaf transformation. This algorithm can avoid “exponential problem”, reduce test generation time and improve test generation efficiency.更多还原