【作者】 李原；

【导师】 赵刚；

【作者基本信息】 四川大学 ， 电路与系统， 2005， 硕士

【摘要】 VHDL是美国所确认的国家工业标准,现在已在世界上许多国家和地区获得迅速的推广和应用。VHDL能形式化地抽象表示电路的结构及行为,支持逻辑设计中层次与领域的描述。VHDL借用了高级语言的精巧结构来简化电路描述,具有电路模拟与验证机制,能够保证设计的正确性,支持电路描述由高层向低层的综合变换,便于文档管理,易于理解和设计重用。因此将VHDL语言作为高级综合的输入描述可以把它作为工业标准的优点与高级综合的自身优点结合起来,其意义十分明显。 同传统高级语言的编译系统一样,VHDL语言的编译系统具有重要的地位,它的质量对于整个高级综合与混合模拟系统的实现与性能有重要的影响。然而,在几乎所有的关于集成电路高级综合理论研究中,对于编译系统中VHDL语言词法分析及语法分析具体实现的讲解都不是很详细,这些又恰恰是影响整个编译系统编译质量好坏的关键技术。所以有必要对它们进行深入细致的研究。也正是因为介绍这方面的资料不多,在前期调研中,每一点进步都需要花费巨大的心血和精力。 本论文的重点是对VHDL编译系统中VHDL语言算法级子集抽取、词法分析器及语法分析器具体编写过程的深入研究。这几点是VHDL编译系统设计中最重要的几点。 本文首先对数字系统设计及高层次综合做了一个整体阐述。简单介绍了编译原理及编译程序结构,还有VHDL语言历史概述及语法介绍。目的是使读者对VHDL编译系统有一个快速而全面的了解。更多还原

【Abstract】 VHDL is a national industry standard that U.S.A affirms, already a lot of countries and regions have got fast popularization and application in the world now. VHDL can abstractly express circuit’s structure and behavior in formalization, it also sustains arrangement and domain’s description in logic design. VHDL borrows the description of high-level language’s ingenious configuration, with which it can refine circuit description. VHDL has circuit simulation and validation mechanism, which makes it can assure the correctness of design and sustain the synthesis transform of circuit description from high-level to low-level. It is easy to manage files and reuse the design. So it has distinctive meaning to make VHDL as the input language in high-level synthesis, because it can combine the virtue of it as industry standard and high-level synthesis itself.The same as traditional advanced programming languages’ compiling system, the compiling system of VHDL language has a very important position too. It has important influence on the realization and performance of the whole high-level synthesis and mix simulation system. However, there is almost no detailed explaining on VHDL lexical analysis and grammatical analysis generation in IC high-level synthesis theory research, while they are just the key techniques which can influence the whole compiling system. So it is necessary to have a deepparticular research on them. Because there are not a lot of materials in this respect, it is very difficult in surveying and studying earlier stage. It needs great efforts to move ahead a little.This paper puts the emphasis on the deep studies of the distilling of VHDL language algorithm-level subset, realization of lexical analyzer and parser analyzer. All of them are important for VHDL compiling system design.A conspectus of digital system design and high-level synthesis are presented first in this paper. It briefly introduces compiling theory, compiling program’s structure and VHDL language’s history and usage. Its purpose is to give the reader a whole understanding of the issues of VHDL compiling system.Then, tnis paper focus on the research of VHDL compiling system design. Here, the writer uses a new software named Parser Generator2.0, this software is easier for using than previous software and it can be installed and run under Windows OS.Studies on several key techniques in VHDL compiling system design are then discussed in turn. Distilling a subset of VHDL language is very important for the generation of lexical analyzer. Because VHDL language itself is based on simulation, all the means it provides are used to build simulation models., so there is a translate procedure when it is synthesized. The paper has a detailed research on VHDL subset distilling and lexical analyzer designing. And the lexical analysis generation program is given in appendix.Finally, the paper discusses the most important part in VHDL compiling system, that is the designing and realization of parser analyzer. Combined with the writer’s development experience, several design tactics are listed in detail. Especially discusses the resolving of conflict.更多还原