简指令微处理器（RISC）的全流程设计

【作者】 赵凯；

【导师】 李惠军；

【作者基本信息】 山东大学 ， 电路与系统， 2005， 硕士

【摘要】 当代超大规模集成电路设计与制造技术日趋成熟。微处理器,特别是嵌入式微处理器的设计实现以其低功耗、高性能之特征发展迅速。简指令CPU(RISC)作为嵌入式系统业已成为SOC(片上系统)研究与开发的技术热点。 本课题完成了基于HIPSII指令系统的32位简指令微处理器全流程设计实现,由系统级硬件描述、仿真与综合验证,直至布局布线及布局优化。 本项研究所实现的一体化设计流程,反映出笔者在超大规模SOC设计思想和设计方法学等领域进行的努力和尝试。特别是在设计流程的组织上所表现出的创新点。本课题所进行的设计流程应用到诸多Synopsys公司的前端和后端设计工具。主要应用到VCS(验证仿真)、DESIGN COMPILE(逻辑综合)、FORMALITY(形式验证)、PHYSICAL COMPILE(物理综合)、FLOOR PLAN COMPILE(布局规划)、CTS(时钟树生成)、PRIMTIME(静态时序分析)、STAR-RCXT(寄生参数提取)及ASTRO(布局布线)等软体。 首先,设计起始于代码级的实现与验证,随后进行了逻辑综合。基于面积约束和时序约束,进行面积和时序的逻辑约束,进入物理设计流程。物理设计流程以物理综合着手,以IO单元、兆单元、行通道生成的次序进行布局规划,完成时钟树的综合,进而使用ASTRO进行布局布线。 本工作在布局布线阶段,对设计进行了静态时序仿真和寄生参数的提取,并根据仿真结果和参数对设计进行了再规划和细化调整,并对逻辑网表和Verilog描述、布图规划之后的网表及门级网表、物理综合后的网表及布图规划后的网表,以及时钟树综合后的网表与物理综合后的网表进行了形式验证。通过对整个流程的调整,对影响信号完整性、串绕和寄生参数的流程进行了重点分析和解决,增加信号线间的间距,采用屏蔽措施,并采用参数提取和参数分析工具来检测易出现信号完整性问题的区域,选择出其中的区域并加以解决。在驱动器选择中,采用缓冲器来分割长线,减小线的长度和耦合电容,将缓冲器输入端的负载降低到单个负载的水平,确保在缓冲器布局布线过程中做较小的改动就可以确保底层规划和优化的实施。笔者在设计流程中加入了静态时序分析步骤,用以处理噪声和延迟问题。将解决串扰和时序的步骤集成到同一流程中。经过反复的试验和设计,更多还原

【Abstract】 Now, the design and manufacture technology of VLSI have been perfected. A great progress has been made in the design of MPU, especially embedded MPU, thanks to its low power consumption and high performance. The research and development of RISC CPU, as embedded system, is vital for the development of SOC (System On a Chip).This subject has completed the whole design of the 32-bit RISC MPU based on the MIPSII instruction system, from the system level hardware description, simulation & synthesis verification and the place and route to the placement optimization.The whole design flow of this subject reflects my attempt in the field of VLSI SOC design methodology, especially in the innovation of the design process organization. Many design tools of Synopsys have been used, including VCS, DESIGN COMPILER, FORMALITY, PHYSICAL COMPILE, FLOOR PLAN COMPILE,CTS, PRIMTIME, STAR-RCXT and ASTRO.Firstly, the design begins with the finish and verification of code level design and the logic synthesis. Based on area constraint and timing constraint, area constraint and timing logic constraint have been finished. Then physical design process is developed. Physical design flow begins with physical compile, followed by the floor plan such as 10 unit and the synthesis of CTS. Place and route have been completed with ASTRO.After the primtime simulation and parastic extraction in the area of place and route, plan and adjustment in detail have been finished according to the simulation result and parameters. Formality of gate netlist, netlist after physical compile, netlist after floor plan, netlist after CTS is finished. By the adjustment of the entire flow, the problems of SI (single integrate), crosstalk and parastic extraction have been analyzed and worked out. Widening the distance between the signal wires, taking shield measures and detecting SI with the parameter extraction and analysis tools. In the selecting of drivers, we take buffers to divide the long wire for the decrease of wires and coupling capacitance. Through decreasing input load of buffer to the singleload, we can ensure the realization of bottom plan and optimization by the small modification in the place and route of buffers. By adding primetime analysis in the design flow, the problems of noise and delay are worked out The procedures solving the problems of crosstalk and timing are put into one flow. Finally, by repeat experiments and designs, the full flow design of RISC has been finished. The research and work of this design have system and operation characteristics and the design foundation of 64-bit RSIC MPU has been made. This research is supported by Semiconductor Manufacturing International Corporation and Trident Multimedia Technologies(Shanghai)Co., Ltd.更多还原