【作者】 郭勇；

【导师】 李仁发；

【作者基本信息】 湖南大学 ， 计算机应用技术， 2005， 硕士

【摘要】 集成电路技术在近10多年来飞速发展。集成电路的集成规模越来越大,已经可以把一个完整的电子系统集成到一个芯片上,即集成电路已经进入了片上系统(SoC)时代。SoC设计的核心技术是IP核。基于IP核的开发给我们带来了诸多的方便。片上总线OCB(on-chip bus)作为一种互联IP核的技术得到了长足发展。 集成电路设计在寄存器传输级的设计方法已经非常成熟。随着集成电路设计复杂程度的日益增长和人们对其设计时效性要求的日益增强,倾向于在更高的抽象层次上如交易级,完成系统的建模、仿真、综合和验证。在交易级完成系统的建模和仿真,可以明显加快速度,同时设计的复杂性更低。内建有支持交易级建模特性的SystemC推动了交易级建模的发展,SystemC的抽象描述能力及其仿真速度也促成了交易级建模的成功。 论文探讨了交易级建模的基本原理和基本方法。研究了SystemC适用于交易级建模的特性。在此基础上,采用交易级建模这一新颖的设计方法,使用SystemC这一功能强大的设计语言,完成了Wishbone这一结构简单、灵活、完全公开、完全免费的片上总线的交易级建模。采用系统级建模仿真工具CoCentric System Studio,针对Wishbone总线协议中两种有代表性的连接方式:点对点连接和共享总线连接,完成了两者的交易级建模。自行设计具有不同行为的主/从设备构建不同的测试环境,完成了Wishbone交易级建模的测试。实验结果表明:点对点连接和共享总线连接方式的交易级模型,符合协议规范,可以有效的用于互连主/从设备,可以应用于片上系统的系统级设计中;依据优先级原则实现的仲裁器可以仲裁具有不同优先级、不同类型的主设备,并且把仲裁器部分作为一个单独的模块设计完成,便于实现不同仲裁策略的,也便于重用仲裁模块;在交易级建模、仿真与在寄存器传输级级相比,具有明显的速度优势。更多还原

【Abstract】 The IC(integrated circuit) technology have been great improved in the last ten years. The integration of IC has become extremely large scale, and a full electric system can be integrated in one chip, called SoC(system-on-chip). The development of IC has stepped into SoC times. The kernel technology of SoC design is based on IP Cores. There is much advantage of this technology. With the development of IP, The OCB(on-chip-bus) used to connect the IP Cores has become the main solution.The IC design method base on RTL has been widely used. With the increasing of design complexity and the demanding of design efficiency, Modeling, simulation, synthesis and validation on the level upon RTL, such as Transaction level, catch people’s attention. Transaction level modeling (TLM) and simulating is much faster and efficienter than doing this at RTL. SystemC, with built in support for TLM, has accelerated the development of TLM methodology. The abstractive description ability of SystemC and the simulation speed promote the success of TLM.The basic theory and method of TLM are discussed in this paper. The property of SystemC, which fits for TLM, is presented. The TLMs(Transaction level Models) of Wishbone is completed based on the novel TLM theory with SystmeC, a powerful language. The WISHBONE System-on-Chip (SoC) Interconnection Architecture is a simple, flexible, open and free design methodology for use with semiconductor IP cores. The TLMs of two typical types of interconnection, point-to-point and shared bus, are finished with CoCentric System Studio. Some master and slave models with different behavior are created and are used to test the TLMs of Wishbone. The result shows that these TLMs of point-to-point and shared bus interconnection conform with the specification and can be used to connect master and slave device efficatively. It is also can be used to the system level design of SoC. The arbiter model with arbitration based on priority is accomplished, which can arbitrate different master and slave with unique priority. It is independent of the other parts of shared bus. So it can be reusable and easily replaced. The result also shows that simulation on transaction level is faster than on RTL.更多还原