八位微处理器IP核设计与研究

【作者】 肖战牛；

【导师】 段哲民；

【作者基本信息】 西北工业大学 ， 电路与系统， 2005， 硕士

【摘要】 随着电子技术的飞速发展,八位微处理器已经成为IP库中的重要成员,而其嵌入式结构正是SoC的一种重要实现技术和方法。 本文在对传统的MCS-51系列单片微控制器进行系统而细致地分析的基础上,找出了制约其性能的关键因素。分析发现,在传统八位微处理器设计中,影响其整体性能的主要原因是:基于累加器的ALU结构、CISC指令体系、时钟系统设计以及系统构架。针对于此,设计了一种类RISC构架的八位微处理器内核。该微处理器内核采用哈佛结构,在ALU模块设计了独立的乘、除法单元,通过采用单周期指令优化指令时序,在内部设置多个快速寄存器及采用硬布线逻辑代替微程序控制的方法,加快了微处理器的速度,提高了指令的执行效率。 考虑到微控制器内核的可移植性,本文对整个微控制器内核采用可综合的VHDL语言编写,并且通过编写测试代码以及约束文件进行了较完整的软件仿真验证和FPGA仿真验证。验证结果表明,该微处理器核的最高时钟频率和指令执行效率均优于标准的MCS-51的三倍以上。更多还原

【Abstract】 With the development of electronic thchnology, IP core become more and more importment in the field of SoC.In order to find out the control factors that limit the performance of the typical 8-bit MCU, a systematical analysis of MCS-51 has been carried out in this thesis. It has been found that the major limitations of typical 8-bit MCU are the ALU structure based on accumulator ,the clock system design and the CISC architecture adopted in MCS-51 design. Then a Top-Down design of 8-bit RISC micro-controller is presented to overcome the limitations of the MCS-51. The core is based on Harvard architecture with 16-bit instruction length and 8-bit data length. The performance of MCU has been improved greatly by introducing signal-cycle instructions, adopt the multiply and divide module independently, setting multiple high-speed working registers and replacing micro-program with direct logic block etc.To keep the MCU core reusable and transplantable, the whole MCU core has been coded for synthesis in VHDL. It is shown from FPGA verification and computer simulation that the MCU core’s maximum clock frequency and instruction efficiency are three times higher than those of typical of MCS-51 chips.更多还原