【作者】 程培星；

【导师】 吴成柯；

【作者基本信息】 西安电子科技大学 ， 通信与信息系统， 2005， 硕士

【摘要】 如今信息技术飞速发展，人们对多媒体，特别是包含有大量信息的数字视频的需求也越来越大。同时，超大规模集成电路技术(VLSI)、可编程逻辑器件(FPGA等)的发展使实时的视频编解码成为可能。 本文深入研究了MPEG-4标准及其建议的视频解码模型。在此基础上针对MPEG-4标准提出了一种基于硬件实现的视频解码系统结构，该结构以现场可编程门阵列(FPGA)为核心，完全用FPGA实现了视频解压算法，同时配合以ARM CPU构建整个系统。该视频编码系统实现了对于分辨率为352×288，25帧／秒符合MPEG4 SP级的ES／PS流的实时解码。用了各种标准测试序列，都得到了良好的主观图像质量。更多还原

【Abstract】 With the rapid development in the areas of communication and computer technologies, digital video plays a more and more important role in information society. At the same time the development of Very Large Scale Integrate circuit (VLSI) and Programmable Logic Device (such as FPGA etc.) makes real-time video compression and transportation possible.This dissertation presents the research result of several issues in video decoding and its hardware implementation. Based on studies an MPEG-4 SP video decoding system is proposed. The system is based on FPGA and ARM. Most procedures in MPEG-4 video decoding system are fulfilled by FPGA, and ARM CPU is used to set up the demonstration system. It realizes real-time video decoding when the input picture resolution is 352 X 288 and its frame rate is 25 frames per second and the input bit rate can be up to 4Mbps. The performance of this system is good.更多还原