高速锁相环集成电路芯片的设计

【作者】 俞宏；

【导师】 韩雁；

【作者基本信息】 浙江大学 ， 微电子学与固体电子学， 2005， 硕士

【摘要】 本课题的目标是设计一个高速锁相环的集成电路芯片。 锁相环自1932年由De Bellescize提出至今，已经得到了广泛的应用与发展。随着半导体工艺技术的提高与成熟，锁相环电路已经以集成电路芯片的形式应用于诸多的产品中。随着科学技术的日新月异，特别是无线通讯、高速处理器等领域，对锁相环电路的性能提出了越来越高的要求，锁相环电路工作在高速环境下已成为当前的一大挑战。 本课题所设计的锁相环路适应高频工作环境，电路结构采用当前的主流结构——数模混合结构的电荷泵锁相环。环路中的鉴相器是数字鉴频鉴相器结构，没有反馈回路，提高了工作频率，并且缓解了传统鉴频鉴相器中死区的产生。电荷泵结构也作了一定的改进，使得电荷注入、电荷分享等寄生效应得到了最大程度上的减缓。压控振荡器采用环路振荡器结构，易于集成而且功耗低。采用了电流驱动逻辑(CSL)结构作为延时单元的压控振荡器具有良好的线性度、较宽的线性范围以及高的工作频率。分频器采用真正的单相时钟TSPC逻辑，可以工作在GHz数量级的频率下。 本设计是采用华润—华晶半导体有限公司CSMC的0.6μm准双阱(twin well)、双层多晶硅(double poly)、双层金属(double metal)的DPDM 5伏标准CMOS工艺实现。利用Cadence的Spectre仿真器进行电路的仿真，Virtuoso平台进行了版图的绘制与验证。6MHz的晶振输入信号，环路最高输出频率为144MHz，分频电路采用了24分频。芯片共有28个管脚(PAD)，包括PAD的面积为2.0mm×2.0mm=4.0mm~2，CPPLL的核心面积为450μm×450μm。更多还原

【Abstract】 This project aims at realizing a chip design of high-speed phase-locked loop integrated circuit. The Phase-Locked loop (PLL), introduced in 1932 by H. de Bellescize, is an electronic device designed to extract the time-domain signals from transmission channels. With the high-speed development of microelectronic and integrated circuit technology, it has been developed from Linear PLL to Digital PLL.Charge-Pump phase-locked loop (CPPLL), which is a truly mixed-signal system belonging to Digital PLL, is widely used as clock generators in a variety of applications, such as microprocessors, wireless receivers, serial link transceivers, disk drive electronics and etc. One of the main reasons for the widely adopted use of the CPPLL is that it provides the theoretical zero static phase offset, and arguably one of the simplest and most effective design platforms. The CPPLL also provides flexible design tradeoffs by decoupling various design parameters such as the loop bandwidth, damping factor, and lock range.Our CPPLL consists of a phase frequency detector (PFD), a charge pump (CP), a passive loop filter (LF), and a voltage-controlled oscillator (VCO). And a divider is used in feedback, in applications where clock multiplications are required. We improved the circuit structures in order to increase the frequency of the CPPLL. The PFD is based on a novel high-speed structure without feedback loops, avoiding the dead zone. The CP’s output is on the drains while its switches are on the sources of MOS transistors, which achieves the high switching speed and reduces the effect of the charge injection and charge sharing. The VCO is a ring oscillator, realized by using a Current Steering Logic (CSL) structure, which makes the CPPLL low jitter, high speed and low power. We also used the True Single Phase Clock (TSPC) CMOS circuit technique to realize the divider, which can operate on a very high frequency.The CPPLL was implemented in a standard CMOS double poly double metal 0.6um technology. It was simulated and analyzed by using Cadence’s Spectre. Its layout and physical verification (DRC/ Extracted/ LVS) were finished by using Virtuoso. The layout area of the whole chip is 2mm × 2mm including 28 PADs. And the area of the core CPPLL is about 450 × 450μm2. The input reference signal is 6MHz from the active crystal oscillator and the output is 144MHz.更多还原