基于CMOS工艺的流水线A/D转换器的实现

【作者】 孔晓彬；

【导师】 张明；

【作者基本信息】 浙江大学 ， 信号与信息处理， 2005， 硕士

【摘要】 随着集成电路工艺与技术的飞速发展，集成电路已经进入系统级芯片(SOC)阶段。高速、低功耗A／D转换器被广泛地用作模拟IP，特别是在通信和视频处理应用SOC中。本文在0.18gm 3.3V／1.8V CMOS数模混合工艺下设计了一个采样精度为10比特，工作频率为40MHz的低功耗流水线A／D转换器芯片。 本文采用了流水线结构以兼顾高速和低功耗要求。整个A／D转换器由9级组成，每级1.5比特，这样的结构级选择很好地平衡了速度与功耗之间的矛盾。另外在设计中还采用了静态功耗很小的动态比较器，其较大的失调误差可以通过数字校正电路得以纠正。运放的设计是流水线A／D转换器设计的关键，本文首先从系统分析入手，根据A／D性能指标要求得到了运放的增益和带宽约束。为同时实现高增益、大摆幅及高带宽，运放的设计在传统的拓扑结构上作了改进。 经仿真验证，该设计在40MHz的工作频率下，输入信号频率为500kHz时的信噪比能达到55.8dB，符合设计要求。更多还原

【Abstract】 With the rapid development of semiconductor technology, integrated circuits has stepped into a new era of SOC. High-speed, low-power A/D converters are widely used as analog IP, especially in SOCs for communication and video processing. In this paper, we proposed a 10Bit 40MHz low-power pipelined A/D converter based on 0.18μm 3.3V CMOS mixed-mode process.Considering the tradeoff between high-speed and low-power, pipelined architecture was adopted. The whole ADC was comprised of 9 stage, 1.5Bit per stage. We also adopted dynamic comparator to mostly eliminate static power. Although such a comparator usually has a large offset, its effect on ADC can be eliminated by digital-error-correction. The design of operational amplifier is the key to implement the pipelined ADC. Stared from system-level analysis, we deduced the constraints of gain and bandwidth from ADC’s specification. Some improvements has been made in the design of operational amplifier to better balance the needs of high-gain, large swing and high bandwidth.According to simulation results, our design can achieve SNR of 55.8dB when operating at 40MHz with an input frequency of 500kHz. Such results meet our requirements.更多还原