芯片设计中的可测试性设计技术

【作者】 张永光；

【导师】 王匡；

【作者基本信息】 浙江大学 ， 通信与信息系统， 2005， 硕士

【摘要】 随着集成电路工艺复杂度和设计复杂度的提高，集成电路的测试变得越来越困难，可测性设计已经成为解决芯片测试问题的主要手段。基于IP(Intellectual Property)核复用的片上系统(Soc)芯片使得测试问题变得更加突出，也对集成电路可测性设计方法和相关的设计流程提出了新的要求。 本文首先简要阐述了集成电路各种常用的测试方法、故障机理和故障模型、与可测性设计相的标准等内容，然后概述了常用的可测性设计技术，如扫描可测性设计，内建自测试，边界扫描等。 接下来结合OR1200芯片的具体电路结构，分析各种可测性设计方法的优缺点，着重研究了实现OR1200芯片可测性设计的方案。此外还采用测试向量生成的方法来检验可测性设计的有效性，结果表明经过可测性设计，采用可测试性设计能很好地达到OR1200芯片测试的要求。 CMOS器件进入超深亚微米阶段，集成电路继续向高集成度、高速度、低功耗发展，使得集成电路在测试和可测试性设计上都面临新的挑战。本文分析了测试和可测试性设计面临的困境；然后讨论了系统芯片(SOC)设计中的测试和可测试性设计，并对测试和可测试性设计的未来发展方向进行了展望。 针对大规模SOC的测试问题，基于具有不同优先级、资源、芯核约束的SOC测试优化模型引入了SOC测试调度用神经网络，同时利用试探性随机搜索技术对神经网络进行了改进。仿真结果表明，采用经过改进过的神经网络不仅能解决SOC的测试问题，而且能够在一个合理的计算时间内找到最优解，在解决SOC测试调度问题方面具有优异的性能。更多还原

【Abstract】 As the complexity of Integrated Circuit design and process is improving, the IC’s test is Becoming more and more difficulty, Design for test (DFT) technology has become the main method to resolve the issue of chip test.The coming of System-on-chip (SoC) era makes the test problem more severe,and puts forward new requirement for the DFT methodology and IC’s design flow.In this paper, the conventional test method is briefly elucidated, as well as fault mechanism, fault model and some standard related IC test. Then some popular DFT methodology is Summarized such as scan chain insertion, Built-in Self Test (BIST) and boundary scan method. The following content is to research how to realize OR1200 chip’s design for testability based on analysis some DFT technology’s characteristic and OR 1200 chip’s circuit structure. Furthermore, Automatic Test Pattern Generation (ATPG) is used to verify the validity of DFT method. The result shows that this method can meet the test requirement.CMOS device dimensions have been down to the very deep submicrometer. Integrated ciructs are going toward higher density,higher speed and lower power dissipation, making new challenges on IC test and design for test. The challenges of test and design for testability are analyzed, Then discusses test and design for testability in SOC design .Furthermore, progress in test and design for testability is to looked forward.To solve the large size SOC test problems, the modeling of Sytem-On-a-Chip (SOC) test optimization has been formulated with different precedence, resource and core constraints.Then,a neural network for SOC test scheduling is presented,moreover, a neural network combined with heuristic algorithm has been developed to solve the large size SOC test problems.As demonstrated by the results that computer implement,the developed method can not only solve the large size SOC test problems, but is also capable of finding the optimal solutions within reasonable computing time. As the result shows, it has good performance in solving SOC test scheduling problems.更多还原