【作者】 司孝平；

【导师】 张红南；

【作者基本信息】 湖南大学 ， 微电子学与固体电子学， 2005， 硕士

【摘要】 国家重点工程项目北京谱仪(BESⅢ)正处于工程预研制和方案初步设计阶段。作为BESⅢ的实时数据获取(DAQ)系统的重要组成部分，BESⅢ的触发判选系统在预研制过程中使用了较多的先进技术，其方案设计的确定必须进行必要的实验研究和测试。VME总线由于其高可靠性和实时性等特点，广泛用于高能探测器的电子学系统，北京谱仪触发判选系统正是构建在VME总线基础上的。同时，由于现场可编程门阵列FPGA设计的灵活性、可重复使用性等特点节省了许多设计环节，缩短了设计和调试的周期，也广泛应用于谱仪电子学设计。 本文所作的工作即是基于VME总线技术和FPGA设计技术，设计了应用于BESⅢ触发判选系统中主触发系统的VME机箱快控制插件(简称CFCTL插件)。主触发系统中的触发控制逻辑和时钟处理逻辑(TTC)是整个BESⅢ触发判选系统的核心。作为TTC的一部分，CFCTL插件的设计对TTC的设计具有重要作用。 CFCTL插件能将触发判选系统的快控制信号L1，CHK，RESET驱动到VME自定义总线上控制一个VME机箱的数据读取，并汇总一个VME机箱的数据读出状态信号RERR、FULL、EMPT信号等报告给触发判选系统的主触发系统，并扇出时钟给子系统。换言之，CFCTL插件能对L1或RERR计数，并且当计数到预置数时，程控地向VME总线发出中断申请，在适当的时刻中断服务程序通知实时数据获取(DAQ)系统开始读取数据，或通知触发判选系统的主触发逻辑处理RERR、FULL有效的情况；此外，CFCTL插件能对来自主触发系统的时钟信号锁相、并能以90°为单位移相，扇出16路LVDS电平的时钟信号给触发判选系统的子系统。 本论文通过所提出的“可预置计数限的计数逻辑”和“有暂停控制的双向计数逻辑”，解决了VME总线主板所能处理的中断的频率与输入信号脉冲的频率不匹配的难题，消除了某些信号与系统时钟异步造成的准稳态，从而实现了CFCTL插件的设计要求。设计制作的CFCTL插件为4层的PCB电路板，是标准的VME单宽6U插件，其主要逻辑功能由一片型号为XC2S50-PQ208C的FPGA芯片实现。对CFCTL插件上的FPGA芯片的计算机仿真结果和CFCTL插件的PCB电路板的测试结果，表明CFCTL插件的设计符合VME总线的时序标准，达到了BESⅢ触发判选系统对它的设计要求。更多还原

【Abstract】 Beijing Spectrometer (BESIII), the National major Project at the Institute of High Energy Physics is approved and now the relative R&D and preliminary Designing are undergoing. As one of the most important parts of the real-time data acquisition (DAQ) system of BESIII, the Trigger System of BESIII , where many new technology will be used ,must be studied and tested carefully before the final design. VME Bus system has high performance of stability and throughput, which is widely used in many electronics systems of High Energy Spectrometer. The Trigger System of BESIII is just based on VME Bus system. At the same time, using the Field Programmable Gate Array—FPGA can simplify the design and shorten the long time needed for PCB design and fabrication, by taking advantage of its flexibility and programmability.Based upon both the VME Bus technology and the FPGA technology , the VME Crate Fast Controlling Module, which will be used in the Global Trigger sysytem , has been designed in this paper. As a part of the the whole circuit of the trigger timing and control logic ( TTC) .which is the heart of the trigger system , this module takes an important part in the design of TTC.The CFCTL Module is able to drive the Fast Controlling signal LI, CHK, RESET upto the User-Defined VME Bus in order to control the read-out of the data from the VME Crate, and gather the read-out state signals RERR,FULL,EMPT from the VME Crate upto the Main Trigger System of the Trigger System, and fan-out clock signals to sub-systems in the Trigger System.In another word, the CFCTL Module is able to count the number of input signals L1,RERR, and send interrupt requests under the control of the programs upto VME bus interrupt handler when the counts equal to the preset counts, then at the right time the interrupt service routine notifys the the real-time data acquisition (DAQ) system of BESIII to begin read the data, or notifys the Main Trigger System of the Trigger System to deal with the situation in the case of RERR or FULL being valid .In addition , the CFCTL Module is able to shift the phase of the input clock by unit of 90 degrees, and fan-out 16 channels of clock signals to sub-systems in the Trigger System.By means of both "the counting logic able to preset the thresholds of the counters" and "the logic for bidirectional counters with the control of pause" brought forward by the author , this paper has solved the puzzle that the frequence at which the VME bus master module can deal with the interruipts doesn’t match that of input signal, and avoid themetastability caused by asynchronization between the system clock and some signals, consequently realize the design demand of the CFCTL module.The chief function of the CFCTL module produced by the author, which is a single width 6U standard VME module, a 4-layer PCB, has been realized mainly by means of a chip of FPGA which type is XC2S50-5-PQ208C. The computer simulation result for the chip of the FPGA on the CFCTL module and the test result for the CFCTL module PCB have indicated that the design of the CFCTL module accords with the timing standard of the VME Bus and the demand from the the Trigger System of BESIII.更多还原