【作者】 费瑞霞；

【导师】 朱恩；

【作者基本信息】 东南大学 ， 电路与系统， 2004， 硕士

【摘要】 论文研究了8B/10B编码中的内在相关性,并在此基础上提出两种编解码方法:一种是基于逻辑设计的编、解码方法,另一种是并行处理算法。通过比较,得出第二种方法逻辑更简单、实现结构更紧凑,而且避免了大扇入、扇出的情况,适合于大规模集成电路。仿真结果证明第二种方法速度较高,用TSMC 0.25um CMOS工艺能够实现不低于300Mb/s速率的编解码。当然,最后流片采用的是TSMC 0.18um CMOS工艺。8B/10B码的主要功能就是大大增加了传输码的0,1转换密度,有利于接收端的时钟恢复。8B/10B码广泛应用于千兆以太网、万兆以太网10 GBASE-X、甚短距离传输(VSR)、光纤通信系统及光纤通信系统背板等。8B/10B码的冗余度相对较高,所以万兆以太网10 GBASE-R和10 GBASE-W标准种采用了另一种编解码方案,即64B/66B编解码方案。64B/66B码本身只是一种码的格式转换,并没有显著增加码的0,1转换密度。所以64B/66B编解码方案包括64B/66B码格式转换、扰码/解扰。64B/66B码冗余度很小,其代价是同步所需时间和资源相对较多。电路采用TSMC 0.18um CMOS工艺设计,通过MPW项目流片。上述两块芯片由于输入/输出管脚数较多,所以都采用了封装测试的办法。芯片封装后,通过PCB板进行测试。更多还原

【Abstract】 This paper is involved in the characteristic of the 8B/10B code, based upon which we advance two methods of coding and decoding. One is the logic relationship to be found out between 8B and 10B, the other is in parallel, the way 8B are coded into 10B or 10B into 8B.In comparison, we find that the latter is better in that its logic is simpler and its structure is compacted with the small numbers of fan-in and fan-out than the former, thus it is beneficial to be integrated in a chip. The results shows that the speed is high, for instance, the circuit can work at least 300Mb/s in TSMC 0.25um CMOS technology. However, the circuit is taped out in TSMC 0.18um CMOS technology. 8B/10B is adopted because the codes have the characteristic of high transition density of 3-8 transitions per 10-bit code-group, which is good to the recovery of the clock in the receiver. 8B/10B is widely used in Gigabit Ethernet, 10 Gigabit Ethernet (10 GBASE-x), VSR, optical communication system and the backboard of the optical communication system.On the other hand, 8B/10B has the high redundancy, which is used for the following: to make error detection more reliable, to separate code-groups for data and control, to provide sufficient transition density for clock recovery, to allow simple code-group synchronization, and to combat poor channel characteristics. So 10 Gigabit Ethernet (10 GBASE-R and 10 GBASE-W) uses 64B/66B coding and decoding, which is the code transform per se without the high transition density and its redundancy is small at the cost of complicated synchronization and the storage, different from 8B/10B. Thus scramble is added to the 64B/66B and descramble is otherwise added before the 64B/66B. The circuit is designed in TSMC 0.18um CMOS technology and taped out in the MPW project.The two chips mentioned above are packaged resulted from a great many inputs and outputs, afterwards the packaged chips are fixed in PCB to be tested.更多还原