DVB-C全数字QAM接收机定时同步模块设计及Verilog实现

【作者】 刘莉琛；

【导师】 朱维乐；

【作者基本信息】 电子科技大学 ， 信号与信息处理， 2004， 硕士

【摘要】 本项目完成的是全数字DVB-C接收机中QAM解调器的定时同步的算法设计以及Verilog实现。整个解调器系统由频率同步，定时同步以及均衡器组成。而定时同步子系统由内插器，滤波器，时钟误差提取，环路滤波以及NCO等模块构成。本文首先介绍了DVB-C系统的相关理论，然后简要阐述了设计中使用的开发工具。在第四章，详细描述了定时同步的原理；第五章，介绍了在Matlab下进行算法设计及软件仿真的结果，并进行分析；在第六章，描述了定时同步模块在Quartus下的Verilog实现。笔者在项目中完成的主要工作有：阅读相关文献资料，了解系统整体原理。与项目组成员合作制定系统框架，制定接口规范。对定时同步模块进行算法设计，软件仿真，结果分析。编写verilog程序实现定时同步模块。更多还原

【Abstract】 The design and verilog realization of the timing recovery in the QAM demodulation of all-digitized DVB-C receiver has been completed in this project. The demodulation system includes timing recovery, frequency recovery and equalization. The subsystem of timing recovery consist of interpolator, timing error detector, loop filter and NCO controller. It realizes the signal synchronization by getting timing error and feedbacks them to control the interpolator. In the paper, the principal of DVB-C theory is introduced firstly, then, the software and platform used in the project are mentioned simply. The theory of timing recovery is recommended detailed in the fourth chapter. In the fifth chapter, the arithmetic design in matlab as well as the simulation and the analysis are discussed. Afterwards, the verilog realization of timing recovery is completed. What penman have done in the project are listed below:Read papers associated with my project and get familiar with basic principal of the system.Make clear the frame of the system with teammates and make the interface criterion.Complete the design of timing recovery in matlab, carry the simulation and analyze the result.Realize the timing recovery in quartus.更多还原