10位80MHz流水线结构模数转换器关键单元设计

【作者】 唐林；

【导师】 杨谟华；

【作者基本信息】 电子科技大学 ， 微电子与固体电子学， 2004， 硕士

【摘要】 本文研究了一个10-bit、3.3V、80MHz采样频率、流水线结构的CMOS模数转换器,详细讨论了其采样保持电路等核心单元的设计。该A/D转换器采用SMIC 0.35um双多晶4层金属的CMOS数模混合工艺流片实现。综合考虑了速度、功耗和动态特性的要求,设计了每级3.5位的三级流水线结构,并使用了数字校正电路对级间误差进行校正。在电路设计中,采用了共源共栅运算放大器保证开关电路处理信号的速度和精度。流水线ADC的模块有采样保持电路、乘法数模转换器、子ADC、数字校正电路、时钟产生电路和时间对齐电路。在Cadence环境下使用HSPICE仿真器对所设计的A/D转换器进行了模拟仿真。在Nyquist采样频率正弦信号输入时,模数转换器的SFDR为70.6dB。芯片面积为4.5*2.4mm2,共28个管脚,采用SOP封装形式。该芯片可以广泛用于视频处理、数据处理等电子技术领域。更多还原

【Abstract】 It’s introduced in this paper a 80MHz, 10bit, 3.3v pipeline architecture CMOS A/D converter. Important blocks such as the Sample and Hold Circuit are analyzed in detail.The chip is designed using SMIC 0.35um 2P4M mixed-signal CMOS process.Considering the speed, power dissipation and dynamic specification, the 3-stage, 3.5bit/stage structure is introduced. A digital calibration circuit eliminates errors between stages. Cascode Op Amps provide the Switch Circuit high speed and good precision. The whole circuit consists of Sample and Hold Circuit, the Multiplicative A/D Converter, the Sub-ADC, the Digital Calibration Circuit, the Clock Generator and the Time Synchronizer.The ADC circuit have been simulated with HSPICE simulator in the Cadence design environment. SFDR is 70.6 dB when Nyquist sampleing sinusoid input signal. The chip’s total die size is 4.5 * 2.4 mm2 and has 28 pins in SOP package.This chip applies to video management and digital operation.更多还原