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基于CMOS工艺的高压MOSFET的研究
The Research of High Voltage MOSFET Based on CMOS Process
【作者】 赫晓龙;
【导师】 姚素英;
【作者基本信息】 天津大学 , 微电子学与固体电子学, 2004, 硕士
【摘要】 数模混合电路的设计日益受到重视。所以如何利用流行的CMOS工艺制造出高压器件并与原有低压电路相兼容已经成为摆在很多研究者面前的一个课题。开发“与CMOS低压电路集成的18V和30V高压MOSFET”是摩托罗拉公司的最新研究项目,主要是为手机中的LCD Driver电路而设计的。本文是对高压MOSFET设计的理论性研究和实践性工作的总结。具体内容主要包括以下几个方面:用工艺和器件模拟软件“ISE”中的模拟程序“DIOS”和“DESSIS”对具有不同场板结构的高压MOSFET进行了工艺模拟和器件模拟。模拟結果说明了对于耐压为18~30V的MOS器件,其击穿点位于栅下靠近表面的漏衬结处。该处电场最强,碰撞电离率最高。模拟结果同时还说明了场板结构可以有效的降低栅下的电场强度,减低碰撞电离率,从而提高该处的击穿电压。利用实验测量验证了模拟结果,并从理论上对场板工作的机理进行了探讨。在高压MOSFET的结构中,利用栅极向漏极延伸而构成场板。利用RESURF理论在靠近漏极一侧做了漂移区。在30V的N型MOSFET中采用了N型埋层结构,并且将N型隔离阱一直做到埋层,与埋层共同构成隔离区,将高压NMOS与其周围器件进行隔离。而对P型MOSFET则主要依靠其本身的自隔离。另外根据上述结构还设计了高压MOSFET的CMOS集成工艺。设计了高压MOSFET的版图,并对版图设计中的主要设计规则进行了说明。根据实际测量结果给出了18V和30V器件设计规则的具体数值。本文对场板工作机理的研究,对高压MOSFET中场板结构的应用具有一定的理论指导作用;版图设计规则的测量对高压MOSFET版图设计具有实际性的指导意义,并为器件模型库中参数化单元的具体参数设定提供了依据。
【Abstract】 The design of analog and digital mixed circuit has been paid more attention increasingly. So many engineers have to face a question, that is, how to produce high voltage devices and make them compatible with low voltage circuits. Motorola Inc. is developing 18V and 30V high voltage MOSFET integrated with CMOS low voltage circuit for the design of LCD Driver circuit used in mobile telephones. Some theoretical research and practical work has been done around the subject. The idiographic contents include several aspects as follows:Simulation programs named “DIOS” and “DESSIS”, which are included in process and device simulation software named “ISE”, are used to do some process simulations and device simulations. The simulation results show that, in the 18V and 30V MOSFET, the breakdown point lies around the junction between the Drain and the Substrate, which is under the gate and close to surface. At that point, electric field is the strongest and impact ionization ratio is the highest. At the same time, the simulation results also show the field plate structure can effectively reduce electric field intensity and decrease impact ionization ratio under the gate. As a result, the breakdown voltage at that point increases. These simulation results have been validated by experiment measuring. And the mechanism of field plate operation has been discussed theoretically.Field plate is formed by poly-silicon extending to the Drain in high voltage MOSFET. Drift region is made at the side of the Drain according to RESURF theory. The structure of N type burial layer has been adopted in 30V N-MOSFET, and N type isolation well is made to contact this burial layer. The isolation well and burial layer make up isolation region so as to separate high voltage devices from other devices around them. On the other hand, the separation of P type MOSFET mainly depends on self-isolation. Besides, CMOS integration process for high voltage has been designed.The layouts for high voltage MOSFETs have been designed and the main design rules are explained. The idiographic data for those rules are given <WP=4>according to the practical measuring results.The research for the mechanism of field plate operation in this paper can offer some theoretic guidance for applying field plate in high voltage MOSFET. Measuring for layout design rule has practical directions to the layout design of high voltage MOSFET and provides basis to setting idiographic parameters of parameterized cells in device model library.
【Key words】 High Voltage MOSFET; Terminal Structure; Field Plate; CMOS;
- 【网络出版投稿人】 天津大学 【网络出版年期】2005年 01期
- 【分类号】TN432
- 【被引频次】2
- 【下载频次】520