【作者】 黎宝峰；

【导师】 颜永红；

【作者基本信息】 湖南大学 ， 微电子学与固体电子学， 2003， 硕士

【摘要】 信息社会的发展，在很大程度上取决于信息与信号处理技术的进步。许多应用系统，如移动电话、数字电视和工业设备等，都需要高性能可编程数字信号处理器。与专用集成电路相比，数字信号处理器由于其可编程特性而更为灵活地应用于实际系统。为满足高端数字系统的需求，高性能数字信号处理器需要具备几十亿次乘累加运算的操作能力。 针对当前高性能数字信号处理器的巨大应用需求，中科院微电子研究所承担了国家863计划重大专项——高性能数字信号处理器的开发。作为此项目的一部分工作，我们设计了一个16位嵌入式定点数字信号处理器，名为μDSP。本论文主要论述了μDSP的设计与验证。 首先，本论文讨论了处理器设计的一般原理，从指令系统、流水线、存储系统三个方面进行了重点阐述，然后进行了数字信号处理器的体系结构设计，其主要特点为：改进的哈佛总线结构、六级流水线、特殊的指令系统和灵活多样的寻址方式等。 在体系结构设计的基础上，根据嵌入式数字信号处理器的设计特点和要求，完成了μDSP的寄存器传输级(RTL)设计。嵌入式设计的特点有：RTL代码的可复用性、尽量不采用全定制设计方法来提高性能、一般不包括各种外围和接口等。 同时，还考虑了可测性设计的问题。在设计的早期就充分考虑到测试的需求，实施可测试性设计，能降低将来测试生成的复杂度、提高故障覆盖率、降低测试成本。在μDSP中，加入了JTAG边界扫描结构和RAM内建自测试逻辑，提高芯片的可测性。 最后，对μDSP的设计进行了严格的功能验证和时序验证。在功能验证上，采取模拟仿真和形式验证相结合的策略；在时序验证上，采用了目前应用最广泛的静态时序分析方法。各种验证方法的综合应用，使得验证工作取得了圆满成功，为整个芯片的投片成功奠定了坚实的基础。更多还原

【Abstract】 The development of information society depends on the progress of information technology and signal processing technology. Many application systems such as mobile phones, digital TV sets and industrial equipments need high performance programmable digital signal processors (DSPs). Compared with application specified integrate circuits (ASICs), DSPs are more flexible to practical applications with the programmability. To meet with the requirement of high-end digital systems, high performance DSPs with the operation capability of more than several Giga multiply-accumulates per second (MACS) are required.Aiming to the great demands for high performance DSPs, a DSPs research project supported by national "863 projects" was carried out in the Institute of Microelectronics, Chinese Academy of Sciences (IMECAS). As a part of this project, we designed a DSPs named DSP which is a 16-bit fixed-point DSPs. This thesis mainly discusses the design and verification of this uDSP.First of all, general principle of processors was described at three basilic aspects: instruction system, pipeline, memory system, and then we designed the architecture of the DSPs. Its main characteristics include: improved Harvard bus structure, six-stage pipeline, special instruction system and flexible addressing mode, etc.Then we designed the uDSP at Register Transfer Level (RTL) based on the design of architecture and according to the requirements of embedded DSPs. The embedded design is characterized by the reusable RTL code, not adopting full custom design to improve performance and excluding various peripheries and interfaces, etc.Design-for-Testabiliry (DFT) was also considered. At the early phase of design, the test requirements should be sufficiently taken into account; this can decrease the complexity of test- vectors generation, enhance the test coverage and reduce costs of test. So, the JTAG Boundary-Scan structure and RAM Built-in Self-Test (BIST) logic have been added into the core of uDSP to enhance the testability of the chip.Finally, the strict functional verification and timing verification was done. On the functional verification, we adopted the strategy of combining simulation with formal verification; on the timing verification, the static timing analysis method was applied. The synthesis of various verification methods brought the verification tasks to success and established the firm basis for the success of tapeout.更多还原