【作者】 蒋科；

【导师】 徐新；

【作者基本信息】 武汉大学 ， 通信与信息系统， 2004， 硕士

【摘要】 多媒体技术获得实用的关键技术之一就是解决视频、音频数字化后数据量大与数字存储媒体和通信网容量之间的矛盾，而其解决的途径就是压缩。为此，国际标准化组织先后制定了视频音频编码的国际标准MPEG-1和MPEG-2，使得基于CDROM的数字视频和数字电视成为可能。而于1999年2月正式公布的MEPG-4(ISO／IEC14496)则可利用最少的数据，获取最佳的图像质量，满足低码率应用的需求。 伴随高压缩率和画质音质的高保真度而来的是算法复杂度的提高，作为MPEG-4的关键技术之一，形状编码的实时性和基于上下文的特性所带来的大运算量对现在的计算机结构而言是一个瓶颈。而专用的集成电路芯片可以根据算法的处理结构，对寄存器、逻辑单元、RAM、控制部件做专门的优化。从而达到比通用处理器高很多的处理能力。鉴此，本文着重研究了MPEG-4形状编码关键算法IP核的设计。 论文从视频压缩的基础知识和集成电路的设计流程入手，基于MPEG-4校验模型(VM)中所阐述的形状编解码算法，采用VC++6.0对其进行了软件模拟分析以作为后续RTL级软核描述的系统建模。在硬件实现上，论文实现了形状编码的两个核心模块—运动估计(BME)和基于上下文的算术编码(CAE)的verilog软核设计。对运动估计引入新的处理单元结构，提出了一种数据扫描方向的设计，配合数据分派技术可以减少存储器读写的操作。对基于上下文的算术编码引入了前导零探测技术，使整个算术编码模块可以实现—个时钟周期编码一个符号的吞吐率。 实验结果表明论文所实现的CAE和BME模块可以适用于完整的形状编码模块的设计。更多还原

【Abstract】 Multimedia information contains huge data. If the data does not be compressed, it is difficult to storage and transfer. The key technique of Multimedia is how to deal with the contradiction between communication networks’ capability and huge data. The approach to handle these problems is compression. International Organization for Standardization (ISO) established MPEG-1 and MPEG-2 successively which make it possible that digital video and digital TV based on CDROM are applied. In Feb. 1999, MPEG-4 (ISO/IEC14496) was issued. The new standard can get the best video quality with few data to meet the requirements of low code rate.The algorithm’s complexity improved with the increase of both the high compression rate and high fidelity of video and audio. Shape coding is the key technique of MPEG-4. The characteristics of shape coding, such as real-time and context based, bring huge burden on computing operation. ASIC can optimize the registers , logic cells and RAM on algothrism and architecture to get better performance than CPU. Our work is aim at the development our own IP core.This paper start with the basic knowledge of video compressing and 1C design flow. The algorithm of shape coding in MPEG-4 verification module (VM) is described by VC++ for behavior modeling. There are two emphases in IP core design in the paper. One of them is the architecture design of binary-shaped motion estimation (BME). The BME architecture mainly comprises processing element (PE) array and the specified address generation unit that includes a new data flow and a new data-dispatch technique. By means of dedicated hardware architecture, the computation of BME algorithm can be efficiently parallelized and pipelined. The other emphase is the architecture of arithmetic coding procedure is modified. Based on leading zeros detection, symbol can be encoded and decoded within one cycle.The result of synthesis and post-stimulation indicates that the BME and CAE module realized in this paper can be used in the design of shape coding module in integrity.更多还原