【作者】 张俊新；

【导师】 曹阳；

【作者基本信息】 武汉大学 ， 通信与信息系统， 2004， 硕士

【摘要】 随着芯片集成度以摩尔定律的快速增长，集成电路工业进入到了SoC时代。整个既包括软件，又包括硬件的复杂混和系统可以被集成到一块包含着数千万个晶体管的芯片上。但是设计能力的增长跟不上复杂度的增长，设计能力与集成度的增长之间存在着一条鸿沟。另一方面，SoC的很大一部分应用于便携式通信、音频和视频处理的消费类电子领域，如手机，MP3播放器。为了尽快占领市场，这类产品要求较短的上市时间。这两个主要因素需要更有效，更快速的新的设计方法的支持。 IP的复用是SoC产品成功开发的关键。为方便用户选择相关IP以及进行SoC的系统级性能评估，必须有效的描述IP。 当前基于平台的设计方法被认为可以有效减少设计风险和缩短上市时间。通过复用针对某一类型应用的平台，可以快速开发出一系列的同族产品。 传统的设计方法由于在设计过程中使用了多种设计语言，不同设计人员之间存在交流的障碍。传统的RTL级设计由于对系统的抽象不够，不能有效处理复杂的SoC系统，在RTL级的仿真性能不能满足需要。SoC是软硬件混和的系统，需要对其进行软硬件协同仿真和验证，目前的软硬件协同仿真在整个设计周期的中后期才开始进行，不利于尽早发现设计中的错误。 SystemC是系统级设计的统一软硬件建模语言，支持从概念到实现的无缝设计流程。使用SystemC使得设计基于统一的语言环境，整个系统得到可执行的功能说明，软硬件协同验证在设计前期就开始，仿真速度更快。 通过系统级建模，提高设计的抽象层次，可以大大降低建模复杂度。事务级建模在RTL级之上，忽略了不必要的细节，把模块之间的通信方式从管脚和信号方式抽象为函数调用。事务级模型可以方便系统工程师评估SoC的体系结构；使SoC软件工程师在设计前期就得到验证软件的快速原型系统，并且为硬件设计工程师提供快速的仿真环境。 本文重点研究了基于SystemC的AMBA规范的总线模型的设计和实现和事务级设计平台的构建。平台主要包括基于AMBA规范的总线模型、RISC CPU模型和存储器模型。通过GUI可以进行设计仿真。该平台具有较好的可扩展性和较快的仿真速度。 时序对比实验表明，总线模型内部达到了周期精确，符合AMBA规范，运行性能接近商业工具平台。接入MP3解码器的实验证明了平台的可扩展性。RISC CPU的存取数据指令的实验证明在该平台上可以进行体系结构性能分析。软硬件协同实验证明在该平台上可以进行软硬件协同验证。更多还原

【Abstract】 With the complexity of the integrated circuit increasing according to the Moore’s law. the IC industry step into the SoC era. An entire heterogeneous system including software and hardware can be integrated onto one single chip, which consist of millions of transistors. However , the design ability lags behind the productivity. There is a huge design productivity gap between them. On the other hand, a large proportion of SoCs are customer products such as portable communication devices, audio or video players, which need very short time-to-market. Hence, more effective design methods are required.IP reuse is the key to successful SoC product development. IP needs proper description for users’ selection and performance evaluation at system level.Platform-based design is considered as an effective method which can reduce risk and time-to-market. By reusing a particular platform, user can develop a family of products quickly.Multiple design languages are used in traditional design flows, there are communication gap between different teams. Traditional RTL design is not able to handle the complex SoC because of slow simulation speed. As SoC is a hardware and software heterogeneous system, hardware/software co-verification and co-simulation is required. Current hardware/software co-verification begins too late in traditional design flow.SystemC is a uniform hardware/software modeling language, which spans from concept to implementation. Using it can produce a executable specification. SystemC enable earlier hardware/software co-verification and faster simulation performance.System level modeling greatly reduces the complexity by raising the abstraction level. Transaction level modeling hides unnecessary details. The communication at transaction level is method calls in comparison with signals and pins at RTL. Transaction level models are used to evaluate the system architecture. SoC software engineers use transaction level models as a fast prototype to verify software early in design flow. SoC hardware engineers also employ transaction level models to build fast simulation environment.This thesis dwells on the design and implementation of AMBA on-chip bus transaction level models and the construction of the transaction level design platform. The platform consists of AMBA on-chip bus models, RISC CPU model and memory module. The platform is easy to extend and have a good simulation performance.The experiments reveal that the AMBA bus models are cycle-accurate internally and compliant to AMBA specifications. The performance is close to the commercial tools. The platform is proved to be extendible by integrating a MP3 decoder module into it. The experiments also reveal that system architecture evaluation and hardware/software co-verification can be performed on the platform.更多还原