网络式仪器总线的研究

【作者】 金小军；

【导师】 宋开臣；

【作者基本信息】 浙江大学 ， 机械电子工程， 2004， 硕士

【摘要】 针对目前各种常用仪器总线在通信方式、实时性、接口复杂性等方面的不足，本文在最新的多点低电压差分信令(M-LVDS，Multipoint Low Voltage Differential Signaling)技术的基础上，提出了一种新的多主结构的仪器总线，即网络式仪器总线的设计方案。总线的物理层基于LVDS／M-LVDS器件，数据链路层采用高速FPGA实现。它不仅实现了真正的多主通信，而且具有通信速率高、实时性强、总线结构简单、数据传输效率高、功耗小等诸多优点。 本文分为七章： 第一章对现有的各种常用仪器总线进行分析比较，指出其中的缺点。接着引入最新的M-LVDS技术，提出基于LVDS／M-LVDS技术的网络式仪器总线的设计思想。 第二章阐述网络式仪器总线硬件平台的设计。首先根据LVDS／M-LVDS技术适用的总线拓扑，确定总线体系结构的设计方案，接着讨论总线数据节点和时钟节点的电路设计，最后探讨高速数字电路的信号完整性设计。 第三章详细阐述了网络式仪器总线协议的设计，包括物理层和数据链路层的设计。最后还提到了应用层的设计要点。 第四章讨论总线管理，阐述了数据传输、流量控制和差错控制在网络式仪器总线中的实现。 第五章阐述总线管理器的FPGA实现。总线管理器主要完成数据链路层以及总线管理的功能，其核心部分是总线数据收发的实现。 第六章描述网络式仪器总线的测试实验，包括总线的一致性和互操作性实验、总线的通信功能实验和总线的通信性能实验，验证了总线设计的正确性。 第七章对全文进行简明的总结，并提出了进一步研究的内容。 本文的创新之处在于提出了利用最新的M-LVDS技术构建网络式仪器总线的设计思想，并充分利用M-LVDS技术的优点独立设计了总线协议，使总线满足实时信号分析仪等高性能仪器在数据通信速率和实时性等方面的较高要求。更多还原

【Abstract】 Aiming at the deficiencies of the popular instrument buses in the communication mode, real time performance, interface complexity, etc., the design scheme of a new, multi-master instrument bus, i.e. the network-stye instrument bus, is presented in this thesis, thanks to the newly developed technology of M-LVDS. LVDS/M-LVDS devices operate as the physical layer of the bus, while the data link layer is implemented by high-speed FPGAs. In the network-stye instrument bus, not only the real multi-master communication is implemented, bus also the advantages of high-speed, high real time performance, simple bus configuration, high transfer efficiency, low power consumption, etc., are attained.The thesis is divided into seven chapters.In chapter one, compares the popular instrument buses, and concludes the respective disadvantages. Then, the newly developed M-LVDS technology is introduced, and the network-stye instrument bus on the basis of M-LVDS is presented.In chapter two, describes hardware system design of the network-stye instrument bus. First, based on the applicable bus topologies of LVDS/M-LVDS, the design scheme of the bus architecture is determined. Then, the circuit design of the bus nodes, including the data node and the clock node is discussed. Lastly, the signal integrity design of high-speed digital circuits is discussed.In chapter three, expounds the design of the bus protocol, including the physical layer and the data link layer. The design notes of the application layer is also discussed.In chapter four, describes the bus management, and discussed the implementation of data transfer, flow control and error control in the network-stye instrument bus.In chapter five, describes the implementation of the bus manager with FPGAs. The bus manager executes the functions of the data link layer and bus management, of which the implementation of data transmit and receive is the core part.In chapter six, explains the experiments of the bus, involving the coincidence test and co-operation test, the test of bus communication functions and the test of bus communication performance. Design correctness is verified with these experiments.In chapter seven, summarizes the whole thesis, and gives expections for further research.The innovation in this thesis is: present the design spirit of the network-stye instrument bus founded on the newly developed M-LVDS technology, and independently design the bus protocol with full use of it, which meets the thirsty requirements of high performance instruments such as real time signal analyzer in data signaling rate, real time capacity, etc.更多还原