高速可配置基2FFT处理器的FPGA实现研究

【作者】 李小进；

【导师】 赖宗声；

【作者基本信息】 华东师范大学 ， 微电子与固体电子学， 2004， 硕士

【摘要】 数字信号处理(DSP)在许多应用领域替代了传统的模拟信号处理系统。FFT作为数字信号处理中的基本模块，是数字信号处理的瓶颈，研究更高性能的FFT处理器一直是国内外的一个研究热点。目前国内外的高速FFT实现方案分为DSP、FPGA和ASIC IP，专用FFT模块的处理速度普遍达到1024点16位字长几十到数百微秒，TI公司的DSP实现1024复数点达到56ps，但需要多片DSP芯片组合，Xilinx公司在800万门的VertexⅡ器件上实现了1μs 1024点FFT处理模块。 本文主要研究高速可配置FFT处理器和以及其FPGA实现，包括从算法设计、算法验证、系统构架设计、各个模块的设计和实现到FPGA的下载实现和测试整个流程。研究设计了具有自主知识产权的高性能可配置的FFT处理器，该FFT处理器具有较高的计算性能，256点的FFT处理仅需9.57μs，与斯坦福大学主页报道的FFT处理器相比，达到了高速运算的目的，可应用于具有实时处理要求的信号处理系统等领域中。作为直接应用，可应用于数字签名运算中。 本文主要的工作包括以下几个部分： 1、对国内外在FFT处理器方面的发展进行了调研，并进行了对比分析。 2、在现有的乒乓结构设计了对称乒乓结构，提高了蝶形运算核的占有率，提高了FFT处理器连续计算的能力。 3、本文所实现的FFT处理器具有可配置性能，最高256点，可根据具体的要求实现2的幂次方的FFT运算，提高了该FFT处理器应用的灵活性和通用性。 4、采用了定点处理内核，设计了块浮点防溢出处理机制，外部计算数据字长为16位，内部RAM存储采用17位，相比1／2直接截尾提高了FFT处理器的计算精度。并进行Matlab进行了系统仿真，在不增加时间延时的基础上提高了数据的运算精度。 5、根据承担的科研项目的需要实现了高速16bits×16bits的乘法器，采用华东师范大学硕士论文高速可配置基2 FFT处理器的FPGA实现研究了修正布斯编码、华莱士压缩树，4:2压缩器和伪4:2压缩器，平方根求和等新型结构。6、设计并实现了整个FFT处理器的电路结构，并用Verilog进行了描述，设计了测试电路，编写了相应的测试向量。等工具对其进行了前仿、后仿真和综合下载实现和测试。硬件描述语言采用VCS、XST7、整个FFT处理器的采用VertexH实现，最高频率可达到112.O07MHz，完 成一次256点的FFT所需的时间为9.57娜，达到了高速处理的预定目标。更多还原

【Abstract】 Digital signal process(DSP) replaces tranditional analog signals process systems in many area. As the basic module FFT is bottle-neck of the signal process. Researching more high speed and performance FFT processor is a hot research spot in the world. At the moment high speed FFT can be realized on DSP, FPGA and ASIC IP. The FFT modules’ speed can reach several ten to hundred millionth seconds. For example, the FFT processor using TI DSP reaches 56 millionth seconds, but several DSP’s are needed. Xinlinx releases its new FFT module based on 800 million-gate VertexII, whose speed achieves 1 millionth second.The Research and FPGA Realization of High-Performance Configurable FFT Processor is presented in this dissertation. It includes the system architecture design and subsystem architecture design, algorithm verification and implementation. At last a test platform was builded by FPGA and PC, and the verification of the FFT processor has been carried out. Computing 256-point FFT using this FFT processor can reaches 9.56 millionth seconds. So this high speed FFT processor in the dissertation can be applicated in high and real time process fields such as digital signal process, telecom system, etc.These works are presented in this dissertation:1. This paper has collected lots of papers related to FFT modules, and analysised these FFT processors.2. A novel structure named symmetrical PingPang structure based on PingPang structures has been presented. So the efficiency of the buttfly core could be highly enhanced.3. Our FFT processor can be configured. The max computing point is 256, and the point that can be set is the power of 2. This character increases the flexibility of the FFT processor.4. An antioverflow mechanism based fixed-point core has been designed. The word length is 16 bits, and the word length of the RAM is 17 bits. Contrastedwith the 1/2 cut-tail, precision has been increased. And this paper has carried out system simulation that has proved that the precision can be enhanced under not adding time-delay.5. A high-speed 16bits*16bits multiplier has been developed, which introduces Modified Booth Arithmetic (MBA), Wallace Tree and 4:2 Compressor, Pseudo 4:2 Compressor and Square Root Carry-Select Adder.6. The whole structure has been developed. The algorithm is realized by VerilogHDL and simulated by VCS, and the testbench has also been designed.7. Having been realized on FPGA of VertexII proves the FFT’s max frequencyreach 112.007MHz. The total time to finish a 256-point FFT is 9.57us .更多还原