【作者】 吴铃铃；

【导师】 张崇巍；

【作者基本信息】 合肥工业大学 ， 检测技术与自动化装置， 2004， 硕士

【摘要】 由于在电子系统中的广泛应用，锁相环已从最初仅为线性模拟锁相环发展到目前以数字锁相环为主。电荷泵锁相环(CPPLL)以其锁定相差小和捕获范围大的优点成为当前数字锁相环产品的主流。 以数模混合为特点的CPPLL设计更为复杂和困难，本文深入分析了CPPLL的构成原理及其电路实现，并给出数模混合的版图设计及一套完整的模拟电路后仿真方案。主要工作有： ．详细讨论构成电荷泵锁相环各部件的工作原理和电路结构。 ．研究SMIC0.18工艺下的CPPLL版图设计方法，主要包括对数字和模拟模块的版图布局，模拟电路抗噪声设计及减小器件失配度的对称性设计研究等。 ．摸索出适用于数模混合电路的具体的后仿真流程，包括寄生参数提取的方法，相关软件的接口问题，以及对电路的调试。 集成电路制造工艺水平和设计水平发展到今天，人们已经将原先的板级系统集成在一个芯片上，系统芯片(SystemOnChip，简称SoC)逐渐成为集成电路设计的主流发展趋势。这样不仅可以提高整个系统的性能，很好地解决板级系统固有的噪声问题，连线延时所带来的速度问题，也将这个系统的成本大大降低。因此很多模拟电路如上电复位电路，模拟数字转换电路(AnalogtoDigital Converter，简称ADC)，锁相环(Phase-LockedLoop，以下简称PLL)电路等也被集成在芯片中，成为大规模集成电路尤其是系统芯片中不可缺少的一部分。采用大规模数字集成电路通常采用的CMOS工艺设计模拟电路成为模拟集成电路设计的重要研究方向之一。更多还原

【Abstract】 PLL (Phase-Locked Loop) has developed from original Linear PLL to now widely used Digital PLL, for their ever-increasing usage in electronic system. Because of the small phase-locked error and big capture scale, Charge-Pump PLL (CPPLL) has been one ofmajor digital PLL products.However, because CPPLL is a mixed signal system, the R&D becomes moredifficult than LPLL. The constructed principle and circuit realization of CPPLL are analyzed in this thesis. The mixed signal layout design and a complete Post Layout Verification of analog IC were also proposed. Three major works are carried out in this work:. The working principle and circuit structure of CPPLL components are discussed in detail.. The design method with SMIC 0.18 for CPPLL layout including the place of digital and analog module, the deal with the noise of analog circuits and the sy mmetry design used to match components is studied.. The Post Layout Verification flow applied to both digital and analog circuits was proposed, which solved include layout parasitic extract, related software interface and debugging of circuit.As the developing of IC design and manufacture process, the board level system is integrated into a chip. SystemOnChip ( SoC) is becoming the primary trend. SoC not only promotes the system performance, but also resolves the problems of noise in board and speed because of line delay. Furthermore, the cost of system is decrease greatly. So a lot of analog circuits such as PowerOn, AnalogtoDigital Converter (ADC), and PLL are integrated in chip as one necessary part of large scale integrated circuit. One of the important R&D aspect is to perform the design of analog with CMOS integrated circuits process which is always used to develop large scale logic integrated circuits.更多还原