基于FPGA的JPEG图像压缩芯片设计

【作者】 贺军；

【导师】 李广军；

【作者基本信息】 电子科技大学 ， 信号与信息处理， 2003， 硕士

【摘要】 JPEG静态图像压缩算法（ISO/IEC 10918）因其对连续色调、多级灰度的静止图象具有优良的压缩特性得到了广泛使用，已成为目前多媒体通信中的图像压缩标准之一。本文探讨了以FPGA（Field Programmable Gates Array）为平台，使用HDL（Hardware Description Language）语言设计并实现符合JPEG静态图象压缩算法基本模式标准的图象压缩芯片。在简要介绍JPEG基本模式标准和FPGA设计流程的基础上，针对JPEG基本模式硬件编码器传统结构的缺点，提出了一种新的改进结构。JPEG基本模式硬件编码器改进结构的设计思想、设计结构和Verilog设计实现在其后章节中进行了详细阐述，并分别给出了改进结构中各个模块的单独测试结果。在本文的测试部分，阐述利用实际图像作为输入，从FPGA的输出得到了正确的压缩图像，计算了相应的图像压缩速度和图象质量指标，并与软件压缩的速度和结果做了对比，提出了未来的改进建议。本课题的JPEG编码器设计，为复杂片上系统（SoC）的设计技术做了有益的探索性尝试，对今后大规模片上系统的设计有着积极的借鉴意义。更多还原

【Abstract】 JPEG is a commonly used digital image compression algorithm officially known as ISO/IEC Standard 10918. JPEG has been widely used in multimedia communication for its excellent performance on compressing continouse tone still image.This thesis consists of designing and implementing a JPEG encoder system that is compatiable with JPEG baseline mode using FPGA (Field Programmable Gates Array) in standard hardware description language Verilog.The conception of JPEG baseline mode and the flow of FPGA design are firstly introduced. The traditional architecture of JPEG baseline mode encoder is presented. Disadvantages of traditional architecture are discussed and an enhanced architecture is proposed. Design principle, structures and Verilog implementations of modules in enhancement JPEG baseline mode encoder are described in detail in follow sections. Each section closed with the test results of respective module in timing verification.The hardware implementation results against real image input are presented and analyzed. Compressed images compressed by FPGA are compared to compressed images compressed by software, focusing on computing time and compress quality. Future research areas are suggested to improve the JPEG encoder performance.This thesis investigates the design technologies of complex SoC (System on Chip) by means of designing and implementing JPEG encoder operating in baseline mode. It provides preliminary study for large scale SoC.更多还原