【作者】 杨永刚；

【导师】 王萍； 侯建文；

【作者基本信息】 天津工业大学 ， 控制理论与控制工程， 2002， 硕士

【摘要】 卫星技术的迅猛发展，信道容量的扩大，要求数传系统能够高速有效的对数据进行实时处理、转发，另外极轨太阳同步气象卫星还具备存储大量信息的固态存储器，即具有延时信息存储、处理和转发功能。由于卫星通信系统能量与带宽受限，采用数字卫星通信信道的特点决定了采用FEC差错控制技术更能有效的保证高效率、高传输码率、低误码率的信息传输。而FEC差错控制技术的关键，也是其最困难实现的，在于如何实现有力的纠错编、译码器。 而目前的空间技术的发展也是一个与地面通信系统相一致的发展趋势，即必须基于一定的空间数据通信协议。目前这一标准化的组织是由NASA、ESA和许多其他国家的空间局成立的空间数据系统咨询委员会(CCSDS)，并推出CCSDS建议的宇航标准。CCSDS标准协议对数据进行高速率打包、多路合成、纠错编码；同时建立了虚拟信道方法，以时分制为基础实现多用户共享信道。另一方面，空间数据通信协议的标准也不是一成不变的。随着通信、计算机以及电子设计与制造新技术在空间方面的不断进步，这些协议也处在不断的发展中。往往因为协议的变化设计就会重新修改，故在设计中就必须有为以后系统升级和改变设计所做的考虑。本论文的设计就是遵循了这样的设计思路，使用的Reed_Solomon纠错编译码是CCSDS推荐的RS[255，223]码，通过高性能FPGA的硬件描述来实现，提高了处理的速度。把地面信息处理系统或某些部分转移到软件(这里的软件是指DSP、ASIC、FPGA里的软件)上来，使系统升级或功能改变基于软件，这样灵活性高且代价小。 数传系统地面处理部分执行的功能基本上是卫星信息处理的反过程，主要完成信息的恢复。在MATLAB环境下可以建立整个系统的数学模型进行功能性仿真。 Reed-Solomon码(简称RS码)是一种重要的循环码，是分组码中纠错能力最强的纠错码，在通信系统和计算机存储系统中应用很广泛。虽然RS码有很多优越的性能，但它的译码过程比较复杂。无论是用硬件方案还是用软件方案，RS码的译码都要占用相对而言较多的资源，因此寻找一种经济实用的译码方案成为纠错编码领域的一个重要课题。RS码的硬件译码器在过去都是用ASIC实现的，研究开发的成本很高。随着可编程器件(FPGA，CPLD)的发展，其性能不断提高而价格不断下降。Altrea公司的APEX20KE系列可编程器件的性能已经达到SOPC(片上可编程系统)的性能，是基于查找表、乘积项、嵌入式存储器的多核结构的第一个PLD器件。本论文用一片300，000门的EP20K300E实现了可纠16个符号错误的8进制的[255，223]RS码译码器，并详细讨论了解扰和RS码的译码理论及硬件译码器在APEX20KE系列FPGA可编程器件上的实现过程。 基于PLD的设计在目前的数字信号处理设计中逐渐成为主流的一种设计技术，在数据的处理的前端尽量采用可编程的硬件来实现一些复杂的算法。这样可以起到使整个信息处理的负荷比较平均，提高了信息处理的效率。更多还原

【Abstract】 The development of satellite and the rapid increase of communication capabilities demand data transmission system has the ability of high speed and efficient data processing and forward in addition the pole track sun synchronization weather satellite still require itself have the solid memory using to storage the big volume information, namely it provide the delay information storage -, process and forward function. Limited by the power and the bandwidth of satellite communication system . The characters of the channel of satellite communication determine that the technique if forward error correction can more efficiently provide better transmission bit rate and lower bit error rate. However the key of FEC technique is how to practically implement the error correction codec, which is also the most difficult to materially realize.However the actual development direction of space technique also is consistent with ground communication technique, namely it must based on a certain data communication protocol of the space . At present the standardization organize is NASA, ESA and the many country’ s space bureau found the CCSDS(Consultative Committee for Space Data System), and recommend the CCSDS prepositional space navigation standard. The CCSDS standard protocol makes the data into high speed packet, multiplexing and the error correction codec; At the same time establish the virtual channel method , implement the multi-user share channel based on the TDM. On the other hand, the standard of data communication protocol of the space is not unalterable. As the communication, computer and the new technique of electronic design and manufacture using in the space field, those protocol also locate in ceaseless development. Often the design must rework because of the change of protocol, hence we must have the consideration for the thereafter system upgrade and change. The design of this paper follow such design thoughts, using the Reed_Solomon error correction codec is the recommendatory CCSDS RS[255 , 223]code, implement it via the high performance FPGA’ s VHSIC Hardware Description Language, enhance the process speed, it can work at the speed of 93Mbps. Thus it transfer the ground information process system or some port to soft (the soft is the soft be in DSP> ASIC and FPGA). It makes the system base on the soft, it has the high flexibility and cost small.The function of the ground information process part of the data transmission system is the reverse process of information processing on the satellite, mainly fulfill the restore of information. The maths model of this system can be founded in the environment of MATLAB and simulate it in function.Reed-Solomon code (for short: RS code) is a kind of important cycle code, and is the best error correction codec of group code , it used widely in communication system and computer storage . Although RS codec has manypredominant performance, its decoding is comparative complexity. Whether using the hardware scheme or software, the RS codec also engross more resource correspondingly, thus searching a kind of economic and applied decode scheme is an important task in the field of the error correction codec. The RS hardware decode was implemented using the ASIC past, but the R&D’ s cost is very high. But the development of PLD is fast at present, the performance is continually improved and the price is continually decline. The FPGA of Altrea’ s APEX20KE series have the same performance as the SOPC, They are the first multi-core PLD based on the lookup table-> product-term and embedded storage block. I used a chip EP20K300E having the 300, 000 gate implemented the RS decode can correct 16 symbol error [255,223]. This paper in detail discussed the implement process of descrambling and RS decoding in the APEX20KE series FPGA.The design technique based on the PLD gradually becomes the mainstream in the digital signals processing design, using the programming hardware to implement some complicated arithmetic in the forward of data process. This can make the load comparativ更多还原