【作者】 徐诺；

【导师】 刘声雷；

【作者基本信息】 合肥工业大学 ， 微电子学与固体电子学， 2003， 硕士

【摘要】 随着集成电路工艺的飞速发展，人们已经可以将原先的板级系统集成在一块芯片上，系统芯片逐渐成为集成电路设计的主流发展趋势。SOC(System On Chip)的出现在很大程度上提高了整个系统的性能，并很好得解决了板级系统固有的噪声问题和板级连线延时所带来的速度问题。它的出现具有划时代的意义，是信息技术发展的一个重要的里程碑。但由于SOC的规模非常庞大，很少有单个公司能够承担整个SOC的开发和维护，加之面市时间(Time-To-Market)的巨大压力，人们逐渐认识到基于预先设计好的IP(Intellectual Property)进行SOC的集成是提升SOC设计效率的非常有效的方法。SOC和IP的出现带动了集成电路产业新一轮的分工，同时也导致集成电路设计方法的巨大革新。 论文首先介绍了SOC及IP产业出现的背景，对IP及基于IP重用的SOC设计方法学以及SOC设计的相关理论和技术进行了探讨。介绍了国际IP标准化组织VSIA(Virtual Socket Interface Alliance)并阐述了IP核的标准化对整个SOC产业和技术发展的重要意义。 论文的主体介绍了一款支持固话短消息功能的SOC——LINE的设计。整个芯片基于IP重用设计方法学设计，其核心是一个32位的嵌入式微处理器—C~*Core(来自Motorola M~*Core)，同时在芯片中集成了RAM、中断控制器、SCI、SPI等功能模块。在顶层设计完成了软／硬件划分和硬件体系架构，根据硬件架构进行功能模块的划分并选用适当的IP。论文第四章着重论述了一个重要的模拟IP——低电压检测复位电路(LVDReset)的设计。LVDReset的基本功能是检测电源电压以防止突然掉电给系统带来的不安全。根据功能及性能的要求，论文给出了电路设计，通过SPICE仿真后还进行了全定制版图的设计和物理验证。第五章给出了基于IP的SOC系统集成，系统集成以预先设计好的IP为起点，对于不同形式的IP除了提供其设计数据之外，还在各个抽象层次的设计基础上提交了相应的信息。系统集成采用主流的数字电路设计流程，通过RTL代码的综合、布局布线和物理验证等步骤完成了整个芯片的物理实现。 论文中设计的芯片—LINE采用TSMC0.25μm四层金属布线的制造工艺，在TSMC0.25μm的多项目晶圆(MPW，Multi-Project Wafer)项目十流片成功，并通过了最终测试。更多还原

【Abstract】 With the development of semiconductor process technology a system on a PCB(Printed Circuit Board)which is composed of several ICs can be integrated into a chip. SOC (System On Chip) can improve the system performance greatly and solve various problems of a PCB system such as noise, speed limit caused by wire delay etc. It makes great sense for the development of information technology. However, as time-to-market pressures and chip complexity grow, current design tools and methodologies are inadequate for developing million-gate SOCs from scratch. Reuse of pre-designed and pre-verified circuit modules, known as IP(lntellectual Property), is the most promising method to bridge the gap between large gate number and designer productivity.After the discussion of SOC design methodology and technique an IP based SOC design is given in the dissertation.LINE is designed for the telephone with short message service function. A 32-bit imbedded microprocessor C*Core (coming from M Core in Motorola) is used as the brain of the system, some additional IPs such as RAM. interrupt controller. Serial Communication Interface, Serial Peripheral Interface are also integrated on the chip. The partition of software/hardware and the architecture design of hardware are completed in the system level design of LINE. The main goal of this dissertation is to present a design of the analog IP. called LVDRcset and the SOC integration of LINE. LVDReset is designed to detect supply voltage in order to protect the chip. After the schematic is verified by Spice simulation, the custom layout and physical verification are made. SOC integration is based on the pre-designed IPs. It is implemented by synthesis and auto place and route. In this process, however, hard IPs must provide enough and accurate information and models in addition to their design data.The design is implemented based on TSMC 0.25m technology with 4 metal. LINE has been taped out through the TSMC MPW (Multi-Project Wafer) project, and passed the final test.更多还原