【作者】 朱小莉；

【导师】 陈迪平；

【作者基本信息】 湖南大学 ， 微电子学与固体电子学， 2003， 硕士

【摘要】 随着集成电路规模的不断增大，集成电路的测试问题变得越来越棘手，于是提出了可测性设计。本文对DSPC50进行了可测性设计。第一章首先介绍了几种主要的可测性设计方法，比较了各自的特点，确定了各自的适用范围。在此基础上得到DSPC50的可测性设计的整体方案，即采用边缘扫描设计提高芯片在板级的可测性，同时用全扫描思想设计芯片核心电路，以降低芯片本身测试的难度，即将芯片的全扫描设计包含入边缘扫描系统。文中第二章按照IEEE.1149标准详细设计了边缘扫描测试系统，相应增加了两个专用数据寄存器，其中一个为扫描链寄存器，一个为扫描子链控制寄存器。第三章以电路中高速的16*16定点乘法器为例，介绍了功能电路的设计、可测性电路的结构、测试码的生成方法。由于片内有SRAM，而SRAM的片外测试比较困难且速度较慢，所以文中第四章采用BIST技术对SRAM进行了可测性设计，完成后可以用正常的工作速度对存储器进行测试。最后一章是对全文的总结，并且对所做的工作的创新之处做了比较详细的介绍，对后续工作的切入做了必要的陈述。对电路进行可测性设计，将缩短产品的开发周期、降低产品的开发成本。更多还原

【Abstract】 Since the evolution of integrated circuits has developed to the point where millions of transistors can be integrated on a single chip, the testing of ICs become more and more intractable. Then design of testability came forth. This paper presents the design for testability of DSPC50. In Chapter One, the mainly-used methods of Design for testability are introduced firstly. Then a comparison is made according to their characters and the application scope of each method is determinate. From that we get the whole scheme of Design for testability of DSPC50, which is using boundary scan to improve the board-level testability of the chip and using full-scan in designing the nuclear circuit to reduce the difficulty of testing the chip. Chapter Two detailedly presents the design of the boundary scan testing system which is in accordance with IEEE. 1149. Correspondingly two special-used data registers are added, one of which is the scanning chain register and the other is the child scanning chain control-register. Chapter Three takes example for the high speed 16*16 fixed-point multiplier used in the circuit to introduce the design of functional circuits, the structure of testable circuits and the method of generating testing codes. Since the chip has interior SRAM and it’s difficult and slow to test SRAM exteriorly, in Chapter Four we use the technique of BIST in Design of testability of SRAM, which makes it possible to test the memory at normal working speed. The last chapter is the summary of the whole paper. It also presents the originality of the work and the plan of later work. By using Design for testability, we can abridge the contriving period and reduce the cost.更多还原