【作者】 李伟良；

【导师】 严晓浪；

【作者基本信息】 浙江大学 ， 电路与系统， 2003， 硕士

【摘要】 随着设计规模和复杂度的增大，使用繁杂的电路仿真进行制造前的时序校验已不切实际。取而代之的是基于静态时序分析(STA)的时序终止(timing sign-off)法，STA估测最坏情况下的电路特性，而与电路的输入模式无关。但随着芯片特征尺寸的不断减小，获取准确可靠的时序收敛变得非常复杂，此时具备分布式RC互连特性的互连线对传统的时序计算模型提出了很大的挑战：首先，分布式RC互连特性使得逻辑门不再只驱动纯容性负载；其次，不断增加的互连线电阻使得电源网格上的电压损耗(IR_drop)变得非常明显；最后，芯片越小越密导致电容耦合增加，造成在门延迟中通常起主要作用的线路延迟更加不确定。因此为了实现可靠的时序分析，时序模型的精确构建变得非常关键。 目前，各类时序模型相继得到提出，但这些模型的实用价值都存在一定的局限性。针对RC负载提出的等效电容分析及有效电压源模型都有很大的计算量，而且计算准确性也不高。而针对IR_drop现象提出的动态时序分析模型则已脱离了STA的算法，况且提出的最坏情况算法也存在很大的缺陷。 针对此，本文在充分分析时序问题及已有模型的基础上，对有效电流源模型(ECSM)作了相应的改进，通过分段线性方法精确地匹配了负载激励点波形的非线性特性，有效地解决了RC负载引起的时序问题。针对IR_drop现象，本文则提出了新的算法，由于该模型基于查表模型和可伸缩多项式的有效结合，因此STA的原算法得到了充分的保留。经过大量的理论分析和实验验证，这些模型能有效地求解深亚微米下的门时延，具有很高的应用价值。更多还原

【Abstract】 As VLSI circuit grows larger and the design task becomes more complex, dynamic simulation with circuit simulators for verifying the timing correctness is not practical under deep subjtnacron designs. Now static timing analysis (STA) which is a very powerful technique is used commonly. STA is pattern independent, implicitly verifies all signal propagation paths in the design, and is applicable to very large designs. However, with the trend of narrower IC feature size, timing analysis is a very challenging task and interconnects with RC characteristic is a big challenge to traditional timing models: Firstly, the load of cell is not the capacitance any more because of the RC interconnects. Secondly, the power supply voltage drop is large and should be considered in an accurate and efficient manner during timing analysis. Finally, as device densities increase, interconnect capacitive coupling with a switching net makes the delay on timing path more uncertain. So it is necessary to have good timing models for timing analysis.Nowadays, lots of models have been presented, but these models have some shortages and can’t be used widely. For example, the effective capacitance model and effective voltage source model offered in file have lots of calculations and provide pessimistic delay approximation which is unacceptable. And dynamic timing analysis including power supply noise doesn’t based on STA and the method of estimation of maximum power supply noise is also pessimistic.Faced with these problems, this file presents a new modified ECSM (Effective Current Source Model) which captures the non-linearity of quasi-capacitive loading by two piecewise-linear approximations after analyzing the traditional timing models. At the same time, this file presents a new timing model considering power supply noise effects. This model keeps the arithmetic of STA based on the effective connection of scalable polynomial with lookup table method. Modeling quality is evaluated both by theoretic and experimental approaches, the result shows that the improved models possesses advantages in terms of accuracy, speed and adaptability to advanced IC technology.更多还原