【作者】 陈志锦；

【导师】 严晓浪；

【作者基本信息】 浙江大学 ， 电路与系统， 2003， 硕士

【摘要】 信息技术的快速发展和集成电路设计的逐步完善，对半导体制造技术提出了更高的要求。集成电路的复杂度越来越高，最小线宽和最小间距变得越来越小。当集成电路的特征尺寸接近光刻机曝光系统的分辨极限时，在硅圆片表面制造出来的电路版图会有明显的畸变，即产生光学邻近效应(OPE—Optical Proximity Effect)，从而严重影响集成电路制造的成品率。为了减少光学邻近效应对集成电路技术发展的影响，工业界提出了光刻分辨率增强技术(RET—Reticle Enhancement Technology)，以使现有的集成电路生产设备在相同的生产条件下能制造出具有更小特征尺寸的集成电路。 象其它的集成电路设计技术一样，光刻分辨率增强技术也需要基于计算机技术的EDA工具的支持。在光刻分辨率增强技术中，需要有光刻模拟过程来支持和指导。光学邻近校正技术(OPC—Optical Proximity Correction)和移相掩模技术(PSM—Phase Shifting Masks)是光刻分辨率增强技术的两种主要技术。不管是采用光学邻近校正技术的掩模图像的预失真或是采用移相掩模技术的掩模相位调整，都要预测在实际光刻条件下掩模在硅片表面的待刻电路层上所成的图像。本文在深入分析了集成电路制造过程的前提下，研究了各个工艺过程的模型，并逐个建立了对应的系统模型，使模拟集成电路的生产过程成为现实。 本文在建立光刻过程的模型中，通过对光刻机的工作原理研究，成功地建立了光刻机照明系统的模型，实现了对曝光过程的模拟，并提出了以双线性系统模型为基础的查表法来加快空间点曝光的模拟；通过对光刻胶特性的研究，实现了高斯模型对光刻胶显影、烘烤过程进行模拟；通过对蚀刻过程的研究，实现了以数据统计为基础的变偏差蚀刻模型(VBM—Variable Bias Model)对蚀刻过程进行模拟。本文还提供了优化方法对各个系统模型进行必要的优化，并用数据统计的方法对优化结果进行统计，以确定最优的模型。更多还原

【Abstract】 The fast development of information technology and the rapid upgrade of design technologies of VLSI increase the burden of the semiconductor manufacturing. The complexity of IC increases, the feature and spacing dimension in the design become smaller. Therefore, the real shapes created on the wafer will not be consistent with the layout when the feature sizes in the design are shorter than half of the wavelength of lithographic light source; in this case, Optical Proximity Effect (OPE) happens. OPE will result in bad performance circuits or even make the circuits invalid, and so it will significantly reduce the IC manufacture yield. Reticle Enhancement Technology (RET) emerges to retain the convention IC manufacture equipments and enable the stepper to create circuit with smaller features. To intentionally and systematically modify the mask to compensate for optical diffraction limit and process non-idealities is the basic idea of RET.Like other technologies used in IC design, RET needs the support of computer technology. Basically, RET has two ways to modify the original layouts. One is to change the shapes of the layout on the mask, which is called Optical Proximity Correction (OPC); the other is to assign different phases to different parts of the mask, which is called Phase Shifting Masks (PSM). Both of the two methods need an EDA tool to simulate the image on the wafer before the modification can be carried out. This paper studies the processes of the 1C manufacture, and focuses on how to build the model of each process.To build the lithographic model, we have studied the theory of how the wafer stepper works, and succeed in realizing the model for the lithographic exposure system. What’s more, in this paper, a bilinear model is realized to speed up the sparse point intensity simulation; a Gaussian model is taken to simulate the behavior of the photomask being exposed and baked; an approach based on statistics is realized to build a Variable Bias Model (VBM) to simulate the etching process; an optimization method is presented to optimize the model parameters for the best accuracy.更多还原