高速逻辑分析仪硬件系统设计

【作者】 戴志坚；

【导师】 王厚军；

【作者基本信息】 电子科技大学 ， 测试计量技术及仪器， 2002， 硕士

【摘要】 逻辑分析仪是最重要的数据域测试仪器之一，随着数字技术和计算机技术的发展，逻辑分析仪获得了广泛的应用和快速的发展。根据本人完成的“400MSa／s逻辑分析仪”项目硬件研制任务，撰写了该论文。该文介绍了ES4541逻辑分析仪的基本工作原理及硬件结构，重点阐述了高速逻辑分析仪数据采集电路以及其驱动软件的设计。“400MSa／s逻辑分析仪”项目是军工型号项目，要求其设计能投入生产实用，仪器能稳定可靠工作并达到要求的性能指标，因此本文还介绍了对ES4541逻辑分析仪进行测试的测试方法及测试结果。 本文第一章是引言部分，介绍了数字系统的基本特征及逻辑分析仪在数据域测试中的应用，国内外逻辑分析仪的发展概况，还介绍了本课题的任务。第二章阐述了高速虚拟逻辑分析仪硬件结构设计，介绍了本逻辑分析仪的硬件总体结构设计，数据采集及控制板与嵌入式计算机的接口。本章还介绍了数据通道的设计及各部分的作用，重点探讨了延迟网络的作用，最后还介绍了触发的作用及其实现的原理以及探头电路的设计原理。 第三章详细阐述了数据采集与存储电路的设计，重点论述了高速数据采集通道的设计，时钟电路及毛刺识别电路的设计。第四章阐述了触发与存储控制电路的设计，介绍了触发与跟踪原理，论述了触发识别电路，触发与存储控制电路的设计，介绍了延迟触发、序列及组合触发以及限定存储的实现方法。第五章介绍了各控制电路在CPLD中的实现，重点阐述了分频时钟电路、译码电路、触发识别电路、限定识别电路、触发与存储控制电路及计数器电路的设计。 第六章介绍了数据采集与控制板的驱动软件的设计，详细阐述了自检程序、数据采集与控制程序以及数据读取与处理程序的设计。第七章介绍了电路的调试及存在的问题，主要介绍了硬件电路的调试方法及过程，调试过程中发现的问题及解决办法，同时介绍了还未解决的问题及其解决方案。第八章介绍了对该逻辑分析仪的整机测试方法及测试结果。最后一章为结论部分，介绍了该逻辑分析仪的特点和不足，以及未来逻辑分析仪的发展方向。更多还原

【Abstract】 Logic analyzer is one of the most important data domain test instruments. Following the development of digital techniques and computer techniques, logic analyzer has a widespread application and gets a rapid development. This paper is the summary of my graduate topic "design of 400MSa/s logic analyzer hardware". The design of the hardware of a high speed logic analyzer (ES4541) and it’s drive software is discussed in the paper. It also introduces the test methodology of ES4541 logic analyzer and test results.The first chapter is a introduction. It describes the basic feature of digital system and logic analyzer’s application in data domain test. It introduces the work of this topic. This chapter also describes the basic theory of sampling with different phase technology. Chapter 2 describes the design of the hardware architecture of a high speed virtual logic analyzer, the interface between the embedded computer and the data acquisition and control board. This part also discusses the design of data channels and theory of trigger. In the last it introduces the theory of probe.Chapter 3 discusses the design of data acquisition and storage circuit. It discusses the design of the high speed data channels, clock circuit and glitch distinguishing circuit. Chapter 4 describes the design of trigger and storing control circuits. It introduces the theory of trigger and tracing, discusses the design of trigger word distinguished circuit, trigger and storing control circuit. Chapter 5 describes the realizing of control circuits in CPLD. This section discusses the procedure that use graphics and AHDL to design clock circuit, decode circuit, trigger word distinguished circuit, limit word distinguished circuit, trigger and storage control circuit and counters circuit.Chapter 6 describes the drive software of data acquisition and control board. It discusses the design of self checking program, data acquisition and control program, data read and processing program. Chapter 7 introduces the adjustment of circuit, the problems find in adjustment and it’s solve methods. Chapter 8 introduces the test methodology of this logic analyzer, and gives the test results. The last chapter is the conclusion. It introduces the performances of this logic analyzer and developing trend of logic analyzer in future.更多还原