【作者】 周干民；

【导师】 刘声雷；

【作者基本信息】 合肥工业大学 ， 微电子学与固体电子学， 2001， 硕士

【摘要】 近年来，微电子设计领域几个重要动向引人注目。其中，功能块电路知识产权（IP，Intellectual Property）化、商品化和标准化的趋势为中国的微电子设计界提供了可能的进入国际市场的切入点。我国的微电子产业如果要赶上或接近世界先进水平，新一代的微电子设计工程师必须掌握使用IP设计方法进行超大规模集成电路设计。 微处理器软核O8CO1由合肥工业大学微电子设计研究所设计成功，课题来源于国家重点科技攻关项目“8位微处理器高层语言描述的研究”，该课题已经通过了由信息产业部主持的技术鉴定。本文作者是该项目组的一名成员，文中所讨论的研究内容都是以该项目为基础。 文中使用了许多EDA工具，象Verilog HDL、Cadence Verilog-XL、Synopsis Analyzer and Avant！COMPASS，来完成整个流程，诸如源代码编写、RTL级仿真、综合、门级仿真等。并对设计结果进行了FPGA硬件仿真。 在课题结题之后，还设计了另外一个软核，IIC总线接口软核，为将来以08C01为核心形成一个系统作准备工作。更多还原

【Abstract】 In recent years, several important tendencies are noticeable in the microelectronics design field.Among them,a trend of intellectual property,commercializing and standardized of functional block, offers a possible entry to international market for China microelectronics. If the microelectronic industry of our country wants to run into or close to the advanced international standards, the microelectronic design engineer of new generation must grasp to use IP?s design method to design the very large scale integration circuit. MPU soft梒ore 08C01 is developed by the Institute of VLSI Design, Hefei University of Technology. The project of developing the core came from a national key program in sciences and technologies, 揝tudy on 8 Bit MPU High Level Language Description? The project has passed the Technical Assessment held by the State Ministry of the Information Technology Industry. The author of the thesis is a member of the project group. And the research work, based on which this thesis is written, is part of the project. The thesis employs several EDA tools, such as Verilog HDL, Cadence Verilog梄L, Synopsis Analyzer and Avant!COMPASS, to going through the entire design flow, like source coding, RTL simulation, synthesis, gate level simulation, etc.A FPGA emulation has been performed either. Having finished the project, I also designed another soft core of IIC梑us interface, prepare to form a system of 08C01 in the future.更多还原