基于RTL描述的组合电路自动测试生成技术研究

【作者】 陈骥；

【导师】 邝继顺；

【作者基本信息】 湖南大学 ， 计算机应用技术， 2001， 硕士

【摘要】 集成电路设计已经广泛使用HDL硬件描述语言作为输入，RTL（寄存器传输级）电路描述介于行为描述和逻辑门级描述之间，既具有电路功能的信息，又能体现电路具体结构实现，这使得基于结构的电路测试方法有可能在RTL级进行推广或改造，同时，行为级的测试方法也有可能与基于结构的测试方法相结合，产生新的测试方法。 近年来，国际上涌现了许多基于结构的或基于行为的RTL测试方法，它们基于各种不同的故障模型和测试理论，取得了一些比较好的效果，但是，都没有得到普遍的接受。过去，国内对电路测试的研究主要集中在门级测试，对RTL测试的研究才刚刚开始。 本文利用RTL电路描述的功能和结构信息，通过对组合电路RTL描述中信号线矢量特点的分析，提出了一种利用矢量特性简化测试的测试方法。该方法以结构测试的测试技术为基础，把功能描述和结构测试生成方法结合，为RTL级电路的测试提出了一些新的思路。 在RTL组合电路结构分析的基础上，本文提出了基本相似电路（BSC，BasicSimilar Circuit）的概念，BSC是通过对电路中信号线矢量位宽的压缩而构造的电路，缩小了电路规模。原电路的测试集可以由BSC的测试集通过一定映射方法得到，从而提高ATPG的效率。通过实验比较和在存储性故障测试生成上的应用，这种测试方法的优点得到了验证。 本文还介绍了一个针对ISCAS 85/89 Benchmark，用于RTL组合电路VerilogHDL描述的编译器，作为RTL电路测试研究的辅助工具。文中分析了Verilog HDL语言和RTL描述的特点，介绍了该编译器解析Verilog HDL描述、创建功能模块类库以及将Verilog HDL的RTL描述转化为无层次分块的门级描述的基本原理和主要问题的解决策略。更多还原

【Abstract】 Hardware description language (HDL) has been widely used in the design of IC. Right between behavior level and gate level, RTL (Register Transfer Level) HDL description involves both the behavior information and the detailed structural implementation of the circuit. This fact has made it possible to promote or reform structure-based test methods at the RTL. At the same time, it is also possible now to produce new test techniques through combining test methods at the behavior level with those based on the structure. In recent years, various behavioral and structural schemes have been proposed. These techniques may target gate-level ATPG or symbolic testing. Some others are based on extracting functional information from circuit. This paper proposed a new methodology of using structurally similar modules constructed by compressing vectors in a circuit. A gate-level test generator is used to generate test vectors for the module under test, then these vectors are adjusted and assembled into system test patterns using a mapping method. This method is mainly based on structure-based test techniques, and also it combines the deterministic algorithm with random test generating techniques. This paper analyzes structural characteristics of signal vectors in combinational circuits with RTL description. Then, this paper presents the concept of the Basic Similar Circuit (BSC), a circuit constructed by compressing the bit-width of vectored vectors in the original circuit. BSC shrinks the scale of the original circuit, thus improving the ATPC efficiency. Test patterns are derived from adjustment and assembling of precomputed sub-circuit test sets. Based on the deterministic algorithm, the ATPG method presented in this paper combines deterministic algorithms and undetermined methods. Experimental results show its advantages. This paper also introduces a Verilog HDL compiler for ISCAS-85/89 Benchmarks as a utility for the study of RTL combination circuits. On the basis of the analysis of features of Verilog HDL and RTL description, this paper shows the method of the construction of the module library and the conversion from RTL HDL description to gate-level description.更多还原