【摘要】 随着计算机技术的快速发展，数据的存储及运算量不断增加，安全、可靠且高效的数据存储及传输愈发重要，在众多加密算法中，AES算法是一种应用广泛的对称加密算法。研究的目标是对AES算法进行改进，令其更适用于硬件实现，以减小面积并提升处理性能。首先，提出了一种轻量化的AES算法AES＿ll,并基于RISC-V指令集架构设计了4种自定义指令，以提高算法的灵活性并降低成本。其次，设计了专用的AES＿ll协处理器并建立了一个可随机生成明文和对应密文的验证平台，以确保AES＿ll算法的硬件实现在不同输入下的可靠性和稳定性。最后，在28 nm工艺下进行了综合，实验结果表明，所设计的AES＿ll协处理器的吞吐率可达到2.976 Gbit/s,面积约为13.97 kgates,在吞吐率和面积比方面占有显著优势，为资源受限且对加解密有较高需求的领域提供了一种良好的解决方案。更多还原

【Abstract】 With the rapid development of computer technology, the volumes of data storage and computation are continuously increasing, making secure, reliable, and efficient data storage and transmission more important than ever. Among various encryption algorithms, the AES algorithm is a widely used symmetric encryption algorithm. The goal of this paper is to improve AES algorithm to make it more suitable for hardware implementation, aiming to reduce hardware area and enhance processing performance. Firstly, this paper proposes a lightweight AES algorithm(AES＿ll) and designs four custom instructions based on the RISC-V instruction set architecture to improve the flexibility of the algorithm and reduce costs. Secondly, a dedicated AES＿ll coprocessor is designed, and a verification platform capable of randomly generating plaintexts and corresponding ciphertexts is established to ensure the reliability and stability of the AES＿ll hardware implementation under different inputs. Finally, synthesis is conducted under a 28 nm process. Experimental results show that the AES＿ll coprocessor achieves a throughput rate of up to 2.976 Gbit/s, with an area of approximately 13.97 kgates, offering significant advantages in terms of the throughput-to-area ratio. The design provides an excellent solution for fields with limited resources and high demands for encryption and decryption.更多还原