【摘要】 高精度时间测量技术广泛应用于高能物理实验和核物理实验中，为满足兰州重离子加速器(Heavy Ion Research Facility in Lanzhou, HIRFL)放射性次级束分离线(Radioactive Ion Beam Line in Lanzhou, RIBLL)中飞行时间探测器(Time of Flight, TOF)对于时间测量高精度、宽动态范围的需要，基于Xilinx ZYNQ 7000全可编程28 nm片上系统，采用“粗计数”和“细计数”相结合的方法，实现了一种通过FPGA(Field Programmable Gate Array)内部逻辑延迟单元Carry4级联构建抽头延迟链的双通道时间数字转换器(Time to Digital Converter, TDC)。设计过程中，针对FPGA内部资源分布引起的“冒泡”问题，采用基于Ones Counter的算法进行优化处理；基于数据高速传输的需求，TDC的时间戳数据通过直接内存访问控制器(AXI DMA)从PL(Programmable Logic)传输到PS(Processing System)端DDR；最终PS端通过TCP/IP协议将数据发送至上位机进行标定和校准工作。经测试，该TDC设计方案500 MHz系统工作频率下最大测量范围为33.5 ms、时间分辨率低于15 ps、微分非线性DNL(Differential Nonlinearity)的范围为[-0.01, 0.03] LSB，积分非线性INL的范围为[-0.01, 0.06] LSB，实现了宽动态范围，线性度良好的高精度时间数字转换器。更多还原

【Abstract】 High-precision time measurement technology is widely employed in high-energy physics experiments and nuclear physics experiments. To meet the demanding requirements of high precision and wide dynamic range for time measurement in the Time-of-Flight(TOF) detectors of the Radioactive Ion Beam Line in Lanzhou(RIBLL) at the Heavy Ion Research Facility in Lanzhou(HIRFL), a dual-channel Time-to-Digital Converter(TDC) has been implemented based on the Xilinx ZYNQ 7 000 fully programmable 28 nm System-on-Chip(SoC). This design adopts a combined method of "coarse counting" and "fine counting," utilizing cascaded Carry4 delay elements within the FPGA to construct a tapped delay line. During the design process, to address the "bubble" issue caused by uneven distribution of FPGA internal resources, an optimization algorithm based on Ones-Counter was implemented. To fulfill the requirements for high-speed data transmission, timestamp data from the TDC is transferred from the Programmable Logic(PL) section to the Processing System(PS) DDR memory via a Direct Memory Access(AXI DMA) controller. Ultimately, the PS section transmits the data to a host computer through TCP/IP protocol for calibration and alignment procedures. Testing results demonstrate that this TDC design achieves a maximum measurement range of 33.5 ms at a system clock frequency of 500 MHz, with a time resolution better than 15 ps. The differential nonlinearity(DNL) ranges from [-0.01, 0.03] LSB, while the integral nonlinearity(INL) ranges from [-0.01, 0.05] LSB. This design successfully realizes a high-precision time-to-digital converter with wide dynamic range and excellent linearity performance.更多还原