【摘要】 设计使用高层次综合语言HLS(High Level Synthesize)来实现图像预测帧内编码模块的功能。帧内预测编码是指利用视频空间域的相关性，使用当前图像已编码的像素预测当前像素，然后将预测残差(当前像素真实值与预测值之间的差值)作为后续编码模块的输入，进行下一步编码处理。HLS实现相比与直接使用verilog和其他的语言来实现，HLS具有开发周期短，可以极大地节省人力成本和时间成本、平台可移植性强以及更便捷的代码迭代等的优势。设计使用HLS实现的对HEIF编码IP中图像预测编码模块，主要用于FPGA中，优化后的IP总占用10795个FIFO和30705个LUT,并且设计在后续优化代码之后缩短了1/3原有编码所需时间，大大提升了编码速率。更多还原

【Abstract】 The design uses high level synthesize(HLS) language to realize the function of image prediction in-frame coding module. Intra-frame predictive coding refers to using the correlation of the video spatial domain to predict the current pixel using the encoded pixel of the current image, and then using the predicted residual(the difference between the real value of the current pixel and the predicted value) as the input of the subsequent coding module for the next encoding process. Compared with the implementation of verilog and other languages directly, HLS has the advantages of short development cycle, great savings in labor cost and time cost, strong platform portability and more convenient code iteration. The image prediction coding module of HEIF encoded IP implemented by HLS is designed, which is mainly used in FPGA. The optimized IP occupies 10795 FIFO, 30705 and LUT, and the design reduces the time required for original coding by 1/3 after the subsequent optimization of the code, greatly improving the coding rate.更多还原