【摘要】 随着微处理器对低功耗与高能效需求的增长，SRAM作为其主要功耗与面积来源，优化SRAM功耗至关重要。降低电源电压是降低功耗的重要方法，但也会严重影响SRAM的读写性能。针对此问题，本文提出了一种新型读写辅助电路结构，该结构可以增强写入能力和加快位线放电速度。此电路通过在写入期间将字线电压先升至欠驱电压后升至过驱电压，以在确保稳定性的同时加强写能力；在读取时，轻微提高字线电压至高于VDD电压，从而加快位线放电速度，增大两条位线电压差值，从而提高SRAM的可靠性。仿真结果表明，提出的结构可以将最小工作电压降低至0.4V，相比未使用辅助电路的结构写能力提升一倍以上，字线打开相同的一段时间，两条位线电压差值可以增加40%以上。相比于传统结构在各自最小电压下功耗可降低20%以上，而相比于在标准电压下的传统结构，功耗可降低70%以上，且只增大3%的面积。更多还原

【Abstract】 With the increasing demand for low power consumption and high energy efficiency in microprocessors,SRAM, as a major source of power consumption and area, optimizing SRAM power consumption is crucial. Reducing the supply voltage is an important method to reduce power consumption, but it also significantly affects the read and write performance of SRAM. To address this issue, this paper proposes a novel read and write assist circuit structure,which can enhance write capability and accelerate bitline discharge speed. This circuit raises the wordline voltage to an underdrive voltage first and then to an overdrive voltage during the write operation, to strengthen write capability while ensuring stability; during the read operation, it slightly raises the wordline voltage above the VDD voltage,thereby accelerating bitline discharge speed, increasing the voltage difference between the two bitlines, and thus improving the reliability of SRAM. Simulation results under advanced processes show that the proposed structure can reduce the minimum operating voltage to 0.4V, more than doubling the write capability compared to a structure without the assist circuit, and increasing the voltage difference between the two bitlines by over 40% during the same wordline activation period. Compared to traditional structures at their respective minimum voltages, power consumption can be reduced by over 20%, and compared to traditional structures at standard voltages, power consumption can be reduced by over 70%, with only a 3% increase in area.更多还原